JPH08148509A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To form highly accurate and reproducible alignment dimension accuracy and wide drain side recess dimension of asymmetric two-step recess structure in high-power GaAs FET. A mask having a silicon oxide film (3) and a silicon nitride film (4), which have selectivity for wet etching, is laminated and patterned to have an opening (5) corresponding to a first recess and a pattern corresponding to a second recess. A layer is formed to cover the portion other than the opening 5 with the photoresist film 6, and the G of the opening 5 is covered.
After forming the first recess 8 on the surface of the aAs operation layer 2,
Only the silicon oxide film 3 is removed by etching to expose the exposed G
The aAs operating layer 2 is dug down to form an asymmetric two-step recess structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a GaAs field effect transistor (hereinafter referred to as "Ga").
(Hereinafter referred to as As FET).

[0002]

2. Description of the Related Art In a GaAs FET for high frequency and high output, a structure called a recess structure in which a gate electrode is formed in a groove formed by etching an operation layer is used in order to improve a gate breakdown voltage.

In order to further improve the breakdown voltage in this structure, it is effective to use an asymmetric structure in which the gate electrode is offset by increasing the distance between the drain-side gate electrode end and the recess end, but the influence of the drain-side surface depletion layer is reduced. Therefore, there is a problem that the output characteristics are easily deteriorated.

Therefore, as described in Japanese Patent Application Laid-Open No. 4-336432, a two-stage recess structure in which an operation layer in a region where a gate electrode is formed is further dug has been proposed.

FIG. 2A to FIG. 2E and FIG.
(C) is a sectional view shown in order of step for explaining the first example of the conventional method of manufacturing a semiconductor device;

First, as shown in FIG. 2A, an n-type GaAs operation layer 2 formed on a semi-insulating GaAs substrate 1 is formed.
A source electrode 12 and a drain electrode 13 are formed on the substrate, and an insulating film 14 is deposited on a surface including the source electrode 12 and the drain electrode 13.
Photoresist film 1 formed on 4 and patterned
5 is used as a mask to etch the insulating film 14 to form an opening 16
To form.

Next, as shown in FIG. 2B, GaAs is used with the photoresist film 15 and the insulating film 14 as a mask.
The first recess 17 is formed by etching the surface of the operation layer to a predetermined depth.

[0008] Next, as shown in FIG.
A 0 nm Ti film 18 is obliquely applied and the photoresist film 16, the insulating film 15 and the first recess 1 exposed in the upper surface of the photoresist film 15 and in the opening 16 are formed.
7 is covered on the side surface on the source electrode 12 side.

Next, as shown in FIG.
Using the mask 8 as a mask, the insulating film 14 on the drain electrode 13 side of the opening 16 is side-etched.

[0010] Next, as shown in FIG.
8 is removed, and the insulating film 14 on the source electrode 12 side and the drain electrode 13 side is
Is side-etched to asymmetrically expose the surface of the GaAs operation layer 2 on the source electrode 12 side and narrow on the drain electrode 13 side.

Next, as shown in FIG. 3A, the exposed surface of the GaAs operating layer 2 is etched using the photoresist film 15 and the insulating film 14 as a mask to form a narrow and deep first recess 17 and a wide recess. A two-step recess having a shallow second recess 19 is formed.

Next, as shown in FIG.
The metal film 10 is deposited on the surface including the metal film 6.

Next, as shown in FIG. 3C, the asymmetric two-step recess 1 is formed by removing the photoresist film 15 and the metal film 10 on the photoresist film 15 by a lift-off method.
A GaAs FET having a gate electrode 11 at 7 is constructed.

As another example, JP-A-4-20673.
A method for manufacturing an asymmetric two-stage recess structure described in Japanese Patent Publication No. 3 (JP-A) No. 3 has also been proposed.

FIGS. 4A to 4E are cross-sectional views showing process steps for explaining a second example of a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 4A, an n-type GaAs operation layer 2 formed on a semi-insulating GaAs substrate 1 is formed.
After forming the source electrode 12 and the drain electrode 13 on the GaAs active layer 2, a first photoresist film 20 is applied on the GaAs operating layer 2 and patterned to form an opening 21 corresponding to the narrow first recess formation region. A pattern corresponding to the wide second recess forming region is formed.

Next, as shown in FIG. 4B, a second photoresist film 22 having an etching rate different from that of the photoresist film 20 is applied to the surface including the photoresist film 20 and patterned to form the opening 21. The opening 23 aligned with is formed. Next, the photoresist films 20 and 2
The recess 17 is formed by etching the surface of the GaAs operation layer 2 exposed to the opening 21 to a predetermined depth using the mask 2 as a mask.

Next, as shown in FIG. 4C, only the photoresist film 20 is removed with an etching solution which dissolves
The surface of the aAs operation layer 2 is exposed.

Next, as shown in FIG. 4D, GaAs including the recesses 17 using the photoresist film 22 as a mask.
The surface of the operation layer 2 is etched to a predetermined depth to form a two-step recess structure having a narrow and deep recess 17 and a wide and shallow recess 19.

Next, as shown in FIG.
The metal film 10 is deposited on the surface of the photoresist film 22 including 3, and the gate electrode 11 is formed in the recess 17 immediately below the opening 23.

Thereafter, the photoresist film 22 and the metal film 10 thereon are removed by a lift-off method to remove GaAs.
Construct an FET.

[0022]

In the first example of the conventional method of manufacturing a semiconductor device, an asymmetric recess is formed by using a method of covering only one side of a gate opening using oblique deposition. In addition, there is a problem that the coatability is poor and shape control is difficult. Further, the width of the recess is set by the side etching amount of the insulating film, so that the dimensional controllability is poor.

In the second example, this point has been improved, and the dimension controllability of the recess is excellent, but the opening of the gate recess and the opening for forming the gate electrode are formed by alignment. In addition, there is a problem that the alignment accuracy between the recess and the gate electrode is reduced. Further, although two different types of resist films are used, it is difficult to obtain complete selection in the exposure and development steps.

An object of the present invention is to form a multi-stage asymmetric recess structure with high precision and high reproducibility by using a GaAs FE.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves the characteristics of T.

[0025]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a GaAs substrate on a semi-insulating GaAs substrate;
A first silicon compound film and a second silicon compound film having different wet etching rates are sequentially deposited and laminated on the surface of the operating layer, and then the second and first silicon compound films are selectively and sequentially anisotropic. A second recess forming region including a first opening corresponding to the first recess forming region having a narrow width by dry etching and the first recess forming region and having a width wider than the first recess forming region. Forming a mask layer having a pattern corresponding to, and patterning by applying a photoresist film on the surface including the mask layer and patterning the second opening including the first opening and being wider than the first opening. A step of forming an opening, and a step of forming a first recess by etching the surface of the GaAs operating layer exposed in the first opening using the photoresist film and the mask layer. When the G and removed by etching the first silicon compound film by wet etching
a step of exposing the surface of the aAs operating layer, and wet etching the exposed surface of the GaAs operating layer using the photoresist film as a mask to form a deep and narrow first recess and a shallower and wider first recess than the first recess. Forming a multi-step recess having two recesses; depositing a metal film on the surface of the photoresist film including the first recess directly below the first opening, and then lifting off the photoresist film and the first recess; 2) removing the silicon compound film and the metal film on the photoresist film to form a gate electrode in the first recess.

[0026]

Next, the present invention will be described with reference to the drawings.

FIGS. 1 (a) to 1 (e) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a 200 nm thick silicon oxide film 3 and a thickness 10 are formed on an n-type GaAs operating layer 2 formed on a semi-insulating GaAs substrate 1.
0 nm silicon nitride film 4 is sequentially deposited and laminated, and RI
Silicon nitride film 4 and silicon oxide film 3 by anisotropic dry etching such as E (reactive ion etching) method.
Are sequentially and selectively etched to form a width 1-2 corresponding to a narrow first recess formation region for forming a gate electrode.
A first opening 5 having a thickness of μm and a mask layer having a pattern corresponding to the second recess forming region including the first recess forming region and having a wide area on the drain electrode side are formed.

Next, as shown in FIG. 1B, a photoresist film 6 is applied to the surface including the mask layer and is patterned to form an opening 7 including the opening 5 and being wider than the opening 5. Form. Next, using the photoresist film 6 and the mask layer, the surface of the GaAs operation layer 2 exposed to the opening 5 is wet-etched to a predetermined depth with a mixed solution of sulfuric acid and hydrogen peroxide to form a recess 8. I do.

Next, as shown in FIG. 1C, the silicon oxide film 3 exposed in the opening 5 is wetted using buffered hydrofluoric acid composed of hydrofluoric acid: ammonium fluoride = 1: 20 (weight ratio). Etching and removing, G under the silicon nitride film 4
The surface of the aAs operation layer 2 is exposed. Next, the GaAs operation layer 2 exposed by the mixed solution of sulfuric acid and the aqueous peroxide solution
The surface of is etched to form an asymmetric two-step recess structure including the recess 8 and the recess 9 in a wide region including the recess 8.

Next, as shown in FIG.
A metal film 10 such as an aluminum film on the surface containing
The metal film 10 is vapor-deposited to a thickness of m to selectively deposit the metal film 10 also in the recess 8 directly below the opening 5.

Next, as shown in FIG. 1E, the photoresist film 6, the metal film 10 on the upper surface of the photoresist film 6, and the silicon nitride film 4 are removed by an organic solvent by lift-off to remove the gate electrode of the recess 8. 11 is formed.
Next, an Au— layer is formed on the GaAs operation layer 2 outside the recess 9.
Each of the source electrode 12 and the drain electrode 13 made of a Ge—Ni alloy is formed.

A high melting point metal silicide film such as a tungsten silicide film may be used in place of the silicon nitride film 4 of the mask layer composed of the silicon oxide film 3 and the silicon nitride film 4. Can be further increased.

[0034]

As described above, according to the present invention, the narrow first recess for forming the gate electrode is formed by the first and second silicon compound films which are formed on the operation layer and which are selective with respect to wet etching. And the second recess having a wide area on the drain side can be formed with good reproducibility in mutual positional accuracy and dimensional accuracy, and the GaAs FET can be formed with good controllability.

[Brief description of drawings]

1A to 1D are cross-sectional views showing a process sequence for explaining an embodiment of the present invention.

2A to 2D are cross-sectional views showing the first example of the conventional method of manufacturing a semiconductor device in the order of steps for explaining the first example.

FIG. 3 is a cross-sectional view for explaining a first example of a conventional method for manufacturing a semiconductor device, which is shown in a process order.

4A to 4D are cross-sectional views showing the second example of the conventional method for manufacturing a semiconductor device in the order of steps for explaining the second example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-insulating GaAs substrate 2 GaAs operation layer 3 Silicon oxide film 4 Silicon nitride film 5, 7, 16, 23 Opening 6, 15, 20, 22 Photoresist film 8, 17, 19 Recess 10 Metal film 11 Gate electrode 12 Source electrode 13 Drain electrode 14 Insulating film 18 Ti film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/41 H01L 29/44 C

Claims (2)

[Claims] 1. Ga formed on a semi-insulating GaAs substrate
A first silicon compound film and a second silicon compound film having different wet etching rates are sequentially deposited and laminated on the surface of the As operating layer, and then the second and first silicon compound films are selectively and sequentially anisotropically formed. Dry etching to form a second recess having a first opening corresponding to a first recess forming region having a narrow width and the first recess forming region and having a width wider than the first recess forming region. Forming a mask layer having a pattern corresponding to the region; and applying a photoresist film to the surface including the mask layer and patterning the photoresist layer to form a second opening including the first opening and wider than the first opening. Forming the opening of the GaAs operating layer, and etching the surface of the GaAs operating layer exposed in the first opening using the photoresist film and the mask layer to form a first opening.
Forming a recess of the GaAs operating layer, etching the first silicon compound film by wet etching to expose the surface of the GaAs operating layer, and exposing the GaAs operating layer using the photoresist film as a mask. Wet etching the surface to form a multi-step recess having a deep and narrow first recess and a second recess that is shallower and wider than the first recess; and the first recess just below the first opening. After depositing a metal film on the surface of the photoresist film including a recess, the photoresist film, the second silicon compound film, and the metal film on the photoresist film are removed by lift-off to form the first recess. And a step of forming a gate electrode. 2. The method according to claim 1, wherein the first silicon compound film is a silicon oxide film, and the second silicon compound film is a silicon nitride film or a refractory metal silicide film.