JPH0316653B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention comprises one or more central processing units (CPUs) having a main storage unit (MSU), a buffer storage (BS), and one or more central processing units (CPUs) having In a data processing system that includes an input/output controller (CHP), the main storage unit (MSU) and central processing unit (CPU), and a storage controller (MCU) between the input/output controller (CHP), The storage control unit (MSU) is used to disable the buffer storage (BS) in the central processing unit (CPU), which is necessary when there is a store access from the input/output control unit (CHP) to the main storage unit (MSU). Regarding serialization control method within MCU).

FIG. 3 is a diagram showing the configuration of the data processing system, in which 1 is the main storage unit (MSU#1~
#n), 2 is a storage control unit (MCU), 3 is a central processing unit (CPU #1 to #n), and 4 is an input/output control unit (CHP #1 to #n).

Generally, data transfer processing performed by input/output devices is
The central processing unit (hereinafter referred to as CPU) 3 stores necessary information on the main storage unit (hereinafter referred to as MSU) 1 (for example, input/output device address, main memory address to which data is to be transferred, amount of data to be transferred, command etc.) and sends a data transfer request to the input/output control unit (hereinafter referred to as CHP) 4.

When CHP4 receives the request from CPU3,
status (CC) along with a recognition signal indicating that it has been received.
is returned to the CPU 3, and upon receiving the recognition signal and the status (CC), the (CPU) 3 terminates the request to the (CHP) 4 and operates to execute other processing.

On the other hand, (CHP) 4 performs a series of data transfer processes according to the above information stored in (MSU) 1 in advance, and after the data transfer process is completed, the state within CHP 4 at the time of completion is as follows: After storing it as a status word in the specified area on the MSU 1, an interrupt signal (eg, end interrupt) is sent to the CPU 3 to report the end of the data transfer process.

When the CPU 3 receives the interrupt, it interrupts the processing that has been going on up to that point, checks the contents of the status word accompanying the data transfer request, determines whether the data transfer has ended normally, and continues. It then operates to perform processing.

In the above data processing system, if
When the CPU 3 is equipped with a buffer storage (BS) 31, one (CPU) (for example, #1) 3 among the plurality of (CPUs) (#1 to #n) 3 is the MSU
(#1 to #n) Perform store access to 1,
The store access is performed by another CPU (for example, #2~
#n) If related to data processing in 3.
The CPU (#1) 3 sends a serialization request signal to the storage control unit (hereinafter referred to as MCU) 2 after making a store access request for the address.

In response to the store access request, MCU2
1 and write data to each other CPU.
(#2 to #n) 3, sends address information for invalidating the corresponding address of the buffer storage and an invalidation instruction signal, and transmits the serialization signal to each other CPU by the serialization request signal. (#2~#n)3
Send to.

CPU that received the serialization signal (#2 to #n)
3 interrupts the process currently being executed and executes a process to invalidate the contents of the address in each buffer storage (BS) 31.

Then, MCU2 transfers the subsequent access of the CPU (#1) that sent the serialization request signal to other CPUs.
It is stopped until the serialization signal is sent to (#2 to #n).

However, from CUP (#1 to #n) 4 to MSU (#1
~ #n) When a store access is performed to 1, the MCU 2 sends a buffer storage (BS) invalidation instruction signal along with address information to each CPU (#1 ~
#n) 3, but since the serialization signal is not sent, each CPU (#1 to #n) 3 actually invalidates the contents of the buffer storage (BS) at the corresponding address. It is not possible to recognize whether the process has been executed or not.

On the other hand, CHP (#1 to #n) 4 is (MSU) (#1
~ #n) When writing the status word to 1, it is necessary to show the latest status word to CPU (#1 to #n) 3, and each CPU (#1 to #n)
It is necessary to invalidate the relevant status word stored in buffer storage (BS) held by the BS.

Also, CHP (#1~#n) 4 is MSU (#1~
No interrupt signal can be sent to each CPU (#1 to #n) 3 until the storage of the status word for #n)1 is completed.

Also, MSU (#1) seen from CHP (#1 to #n) 4
~ #n) A status word storage request for 1 is sent to MCU2
It appears as if the request has ended when the request is received, but in reality, it may remain in (MCU) 2 for a while depending on the state of MSU (#1 to #n) 1.

Therefore, until now, in anticipation of these situations,
Each CHP (#1 to #n)
Since the interrupt signal was sent by counting the time in the CPU 4, there were cases where the interrupt signal could not be sent to the CPU (#1 to #n) 3 for a while even after the storage of the status word was completed. Yes, each CHP (#1~
An efficient interrupt transmission method has been awaited when #n)4 stores a status word for MSU (#1 to #n)1.

[Conventional technology]

From the aforementioned CHP (#1~#n) 4 to MSU (#1~
#n)1, the conventional method of requesting store access to the MCU 2 when a state word store access is made and the buffer invalidation processing operation will be explained with reference to FIG.

In FIG. 2, 2 and 4 are the same as those explained in FIG.

In this diagram, the CPU is
(#1 to #n) are shown as two CPUs 31 and 32, and CHP (#1 to #n) is shown as one CHP 4.

First, for comparison, there is one for MCU2.
When a store access request is received from CPU31,
The operation of the invalidation process (hereinafter referred to as BS invalidation process) for the contents of the address in the buffer storage (BS) for other CPUs 32 will be explained.

Now, there is a store access from CPU31 to MSU1, and the store access is performed by another CPU32.
where it relates to data processing in (e.g.
(e.g. when executing test & set commands), the CPU 31
A serialization request signal (SRQ) is sent to the MCU 2 along with an MSU access request and address.

In the MCU 2, the "address translation and MSU access request acceptance unit" 211 accepts the access request, performs logical address-real address translation, and then performs priority control with other access requests in the priority circuit 23, giving priority to the access request. Only the most frequent access requests are selected and the timing control unit 24
and according to the predetermined timing,
An activation signal and an address are sent to the MSU 1, and the address of the access concerned and the serialization request signal (SRQ) are input as a buffer invalidation instruction to the buffer invalidation processing section 25 having a queue structure. At this time, the above serialization request signal (SRQ)
is input to the serialization processing flag unit 2511 of the buffer invalidation processing unit 25.

The buffer invalidation processing unit 25 sequentially takes out the input buffer invalidation instructions and sends them to other CPUs 32.

The CPU 32 that received the buffer invalidation instruction
When the above serialization processing flag (SRF) is identified, all processing that is being executed at that time is interrupted, and
The BS invalidation process is executed, but when the flag is not present, the instruction for the BS invalidation process is held and the (BS) invalidation process is executed during free time.

That is, the BS invalidation process performed by another CPU 32 in response to a store access by a certain CPU 31 is performed independently of the process performed by the CPU 31 that performed the store access.

However, if a status word store access is made from the CHP 4 to the MSU 1, for example after the data transfer operation is completed, all CPUs 31 and 32 are accessed from the buffer storage (BS) where the status word is stored. ) address, it is necessary to perform the above BS invalidation process.

At this time, in the conventional method, only the MSU access request signal and the corresponding address are sent to the MCU 2, and when the "address translation and MSU access request receiving unit" 22 in the MCU 2 receives the request, the corresponding logical address is sent as described above. is converted into a real address and then sent to the priority circuit 23. If the priority is high, the timing control unit 24 is activated, and an activation signal and address to the MSU 1 are sent out according to predetermined timing. At the same time, only the address of the access is input to the queue-structured buffer invalidation processing unit 25 as buffer invalidation processing.

Since the CHP 4 does not receive the BS invalidation process end signal from the MCUP 2, it operates within its own CHP to send an interrupt signal to the CPUs 31 and 32 at appropriate timing as described above.

[Problem to be solved by the invention] Therefore, in the conventional system, when the storage of the status word from the MCU 2 to the MSU 1 is completed, and when each
Even if BS invalidation processing is executed in CPU3,
Until the timer in CHP4 overflows,
There was a problem that interrupts could not be sent to each CPU3.

In view of the above-mentioned conventional drawbacks, the present invention provides a certain CHP4
When accessing MSU1 to store the status word, it adds a serialization request signal to the address and sends it to MCU2, where MCU2 performs the following steps:
When the above serialization request signal is detected and a BS invalidation instruction for the store access is sent to each CPU 3, a serialization signal is sent to each CPU 3, and a BS invalidation process end signal is sent to the corresponding CHP 4. In this way, the purpose is to provide a method for efficiently interrupting the CPU 3.

[Means for solving problems]

And this purpose is the input/output control signal (CHP)
A storage control unit (MCU) for storing the status word in the main storage unit (MSU) upon completion of data transfer.
When sending out a storage request to the status word, a control signal indicating a final storage request for the status word is added and sent. means for recognizing a control signal indicating a control signal, and after the storage processing of the data requested to be stored when the control signal is recognized, each central processing unit (CPU) is configured to send the buffer storage (BS) to the corresponding address.
and a serialization signal instructing immediate execution of the invalidation process based on the invalidation instruction and prohibition of reference access until the completion of the process,
The input/output controller (CHP) is equipped with a buffer invalidation processing means for sending a final storage request end signal to the input/output controller (CHP), and upon receiving the final storage request end signal, the input/output controller (CHP) immediately returns the data This is achieved by the serialization control scheme of the present invention which sends a termination interrupt signal to the processing unit (CPU).

[Effect]

That is, according to the invention, MSU1 from CHP4
When sending the final storage request for the status word to the MCU 2, by adding a serialization request signal (SERQ) and sending it, the MCU 2 sends the storage request with the serialization request signal (SERQ) added and the previous storage request. (CHP) 4 (a series of storage requests associated with the storage operation of interest), and also processes the buffer storage (BS) associated with the storage request with the serialization request signal (SERQ) added. ) After sending the invalidation instruction to CPU3, at the time when the serialization signal is sent to CPU3, a BS invalidation processing end signal (SER END) is sent to CHP4, and when the CHP4 receives this end signal, it is triggered. In this case, it operates to interrupt CPU3, so
This has the effect of allowing interrupt operations to be performed reliably and without wasting time.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. The same symbols as in FIG. This is a serialization control circuit necessary to implement the present invention.

Even when the present invention is implemented, for example,
The operation of BS invalidation processing for other CPUs 32 when a store access is made from CPU 31 to MSU 1 is the same as the conventional method, so here we will explain how to perform BS invalidation processing from CHP 4 to MSU 1, for example, after data transfer is completed. , the operation will be described when it is necessary to perform store access to the state word and invalidate the state word stored in the buffer storage (BS) in the CPUs 31 and 32.

First, in order to store the status word in the MSU 1, the CHP 4 sends an MSU access request and address information to the MCU 2, and also sends the serialization request signal (SERQ).

In the MCU 2, the above-mentioned access request and address information are received by the "address conversion, MSU access request receiving unit" 22, and after converting the logical address into a real address, the information is transferred to the priority circuit 2.
Send to 3.

On the other hand, the serialization request signal (SERQ) accompanying the store access of the state word is sent to the flip-flop 26.
and sends it to the priority circuit 23.

The priority circuit 23 performs priority control over other access requests, and when the store access has a high priority, activates the timing control unit 24 and sends an activation signal to the MSU 1 at a predetermined timing. and send the address,
The address of the store access and the serialization request signal (SERQ) are inputted to the queue-structured buffer invalidation processing unit 25 as a buffer invalidation instruction. At this time, the serialization request signal (SERQ) is sent to the serialization processing flag section 2 of the buffer invalidation processing section 25.
513.

The buffer invalidation processing unit 25 sequentially takes out the input buffer invalidation instructions, and
It is sent to the CPUs 31 and 32.

In the sequential control circuit of the present invention, the output of the serialization processing flag 2513 is output to the OR circuit 281 and 2.
At 82, the logical sum is taken and the serialized signal is sent to the CPU.
31 and 32, the flip-flop 27 is set and the flip-flop 26 is reset by the output signal, and the output of the flip-flop 27 is sent to the CHP 4 as a BS invalidation processing end signal (SER END). Function.

When the CPUs 31 and 32 detect the serialization signal, they interrupt the processing currently being executed and execute BS invalidation processing for the address.

When the CSHP 4 detects the BS invalidation process end signal (SER END), it assumes that the status word store access to the MSU 1 has been completed and operates to issue an interrupt signal to the CPU 31 or CPU 32.

In this way, CHP4 in MCU2,
It is possible to receive an end signal from the MCU 2 indicating that all state word store accesses issued by the user have been completed and send an interrupt signal to the CPU 31 or CPU 32, which improves the efficiency of state word store accesses. Interrupts can be made.

〔Effect of the invention〕

As explained in detail above, in the serialization control method of the present invention, when the CHP 4 sends the final storage request for the status word to the MSU 1 to the MCU 2, the serialization request signal (SERQ) is added and sent. As a result, the MCU 2 processes all the storage requests to which the serialization request signal (SERQ) is added and the previous storage requests from the CHP 4 (a series of storage requests associated with the storage operation in question), and also processes the storage requests mentioned above. After sending a buffer storage (BS) invalidation instruction along with a storage request with a serialization request signal (SERQ) to the CPU 3, at the time the serialization signal is sent to the CPU 3,
BS invalidation processing end signal (SER) to CHP4
END), and (CHP) 4 operates to interrupt (CPU) 3 upon receiving the end signal, so it is reliable and does not waste time. This has the effect of allowing interrupt operations to be performed without interruption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram explaining a conventional method of store access request operation and buffer invalidation processing operation, and FIG. 3 is a block diagram of an embodiment of the present invention. 1 is a diagram showing the configuration of a related data processing system. In the drawing, 1 is a main storage unit (MSU), 2 is a storage control unit (MCU), 3, 31, and 32 are central processing units (CPU), 4 is an input/output control unit (CHP),
211, 212, 22 are “Address translation, MSU
23 is a priority circuit; 2
4 is a timing control unit, 25 is a buffer invalidation processing unit, SRQ and SERQ are serialization request signals, and SER
END indicates a BS invalidation processing end signal.

Claims (1)

[Claims] 1. One or more central processing units (CPUs) having a main storage unit (MSU) and buffer storage (BS), and one or more central processing units (CPUs) that are specified according to instructions from the central processing units (CPUs). After executing the data transfer process between the input/output device and the main storage unit (MSU), a status word is stored in a specific location on the main storage unit (MSU), and an end interrupt is sent to the central processing unit (CPU). one or more input/output control units (CHPs) that perform
Controls access to the main storage unit (MSU) from the central processing unit (CPU) and input/output control unit (CHP), and controls the access to the main storage unit (MSU) from the central processing unit (CPU) or input/output control unit (CHP). A data processing system comprising: a storage control unit MCU that sends an instruction to invalidate the address of the buffer storage (BS) to a central processing unit (CPU); When sending a storage request to the storage control unit (MCU) for storing the status word in the main storage unit (MSU) upon completion of the process, a control signal indicating a final storage request for the status word is added. the memory control unit (MCU), means for recognizing a control signal indicating a final storage request sent by the input/output control unit (CHP); and a storage request when the control signal is recognized. After completing the storage process of the data being stored, instruct each central processing unit (CPU) to invalidate the buffer storage (BS) for the address, immediately execute the invalidation process based on the invalidation instruction, and perform the process. buffer invalidation processing means for transmitting a serialization signal instructing prohibition of reference access until the end of the input/output control device (CHP) and a buffer invalidation processing means for transmitting a final storage request completion signal to the input/output control device (CHP); ) is characterized in that upon receiving the final storage request termination signal, a termination interrupt signal is immediately sent to the central processing unit (CPU) that has commanded the data transfer.