JPH0316736U - - Google Patents
Info
- Publication number
- JPH0316736U JPH0316736U JP7842289U JP7842289U JPH0316736U JP H0316736 U JPH0316736 U JP H0316736U JP 7842289 U JP7842289 U JP 7842289U JP 7842289 U JP7842289 U JP 7842289U JP H0316736 U JPH0316736 U JP H0316736U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- signal
- pmosfet
- source
- nmosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案に係るブレーク・ビフオア・メ
ーク制御回路の一実施例を示す構成図、第２図は
本考案の使用例を示す構成図、第３図は本考案の
ブレーク・ビフオア・メーク制御回路の動作を説
明するための各部の動作波形図、第４図は本考案
の他の実施例を示す図、第５図は従来のブレーク
・ビフオア・メーク制御回路の一例を示す構成図
、第６図は従来例における動作波形図、第７図は
従来のブレーク・ビフオア・メーク制御回路にお
けるインバータの構成例を示す図である。
１１，１１ａ，１１ｂ……ＰＭＯＳＦＥＴ、１
２，１２ａ，１２ｂ……ＮＭＯＳＦＥＴ、１３，
１３ａ，１３ｂ……コンデンサ、１４，１４ａ，
１４ｂ……インバータ、１５，１５ａ，１５ｂ…
…ナンドゲート、１６……抵抗、１７……ＮＭＯ
ＳＦＥＴ。
Fig. 1 is a block diagram showing an embodiment of the break-before-make control circuit according to the present invention, Fig. 2 is a block diagram showing an example of use of the present invention, and Fig. 3 is a block diagram showing an example of the break-before-make control circuit of the present invention. FIG. 4 is a diagram showing another embodiment of the present invention; FIG. 5 is a configuration diagram showing an example of a conventional break-before-make control circuit; FIG. 6 is an operating waveform diagram in a conventional example, and FIG. 7 is a diagram showing an example of the configuration of an inverter in a conventional break-before-make control circuit. 11, 11a, 11b...PMOSFET, 1
2, 12a, 12b...NMOSFET, 13,
13a, 13b... Capacitor, 14, 14a,
14b...Inverter, 15, 15a, 15b...
...Nand gate, 16...Resistance, 17...NMO
SFET.
Claims (1)
印加されると共に基板がソース側に接続されたＰ
ＭＯＳＦＥＴと、 このＰＭＯＳＦＥＴと縦続接続され、ゲートに
バイアス信号を受け、ソースと基板がコモンライ
ンに接続されたＮＭＯＳＦＥＴと、 前記ＰＭＯＳＦＥＴとＮＭＯＳＦＥＴの共通接
続点と電源あるいはコモンライン間に接続される
コンデンサと、 ＰＭＯＳＦＥＴとＮＭＯＳＦＥＴの共通接続点
に現われる信号を反転するインバータと、 このインバータの出力とＭＯＳＦＥＴのゲート
に入力される信号とのアンドをとるアンドゲート
と、 ドレインとゲートが接続されそこに抵抗を介し
て電源電圧が印加され、ソースと基板がコモンラ
インに接続され、ドレインより前記ＮＭＯＳＦＥ
Ｔのゲートに与えるバイアス信号を発生するバイ
アス回路 からなり、前記ＰＭＯＳＦＥＴのゲートにスイ
ツチ駆動信号が与えられたとき、ブレーク・ビフ
オア・メイクとなるスイツチ制御信号が前記ナン
ドゲートより得られるように構成されたことを特
徴とするブレーク・ビフオア・メーク制御回路。[Claims for Utility Model Registration] A P-type device in which an input signal is received at the gate, a power supply voltage is applied to the source, and the substrate is connected to the source side.
A MOSFET, an NMOSFET connected in cascade with this PMOSFET, whose gate receives a bias signal, and whose source and substrate are connected to a common line, and a capacitor connected between the common connection point of the PMOSFET and NMOSFET and the power supply or common line. , an inverter that inverts the signal that appears at the common connection point of the PMOSFET and NMOSFET, an AND gate that ANDs the output of this inverter and the signal that is input to the gate of the MOSFET, and the drain and gate are connected to each other through a resistor. A power supply voltage is applied to the NMOSFE, the source and the substrate are connected to a common line, and the drain is connected to the NMOSFE.
a bias circuit that generates a bias signal to be applied to the gate of the PMOSFET, and is configured such that when a switch drive signal is applied to the gate of the PMOSFET, a switch control signal that is a break-before-make is obtained from the NAND gate. A break-before-make control circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7842289U JPH079457Y2 (en) | 1989-07-03 | 1989-07-03 | Break-before-make control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7842289U JPH079457Y2 (en) | 1989-07-03 | 1989-07-03 | Break-before-make control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0316736U true JPH0316736U (en) | 1991-02-19 |
| JPH079457Y2 JPH079457Y2 (en) | 1995-03-06 |
Family
ID=31621680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7842289U Expired - Lifetime JPH079457Y2 (en) | 1989-07-03 | 1989-07-03 | Break-before-make control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079457Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015002507A (en) * | 2013-06-18 | 2015-01-05 | 凸版印刷株式会社 | Switch circuit |
-
1989
- 1989-07-03 JP JP7842289U patent/JPH079457Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015002507A (en) * | 2013-06-18 | 2015-01-05 | 凸版印刷株式会社 | Switch circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079457Y2 (en) | 1995-03-06 |
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