JPH03169042A - Chip tray for semiconductor element - Google Patents
Chip tray for semiconductor elementInfo
- Publication number
- JPH03169042A JPH03169042A JP1310128A JP31012889A JPH03169042A JP H03169042 A JPH03169042 A JP H03169042A JP 1310128 A JP1310128 A JP 1310128A JP 31012889 A JP31012889 A JP 31012889A JP H03169042 A JPH03169042 A JP H03169042A
- Authority
- JP
- Japan
- Prior art keywords
- chip tray
- semiconductor chip
- chip
- cleanliness
- degree
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000003973 paint Substances 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 abstract description 9
- 230000003749 cleanliness Effects 0.000 abstract description 6
- 230000005611 electricity Effects 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 3
- 230000000694 effects Effects 0.000 description 4
- 239000003086 colorant Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
Landscapes
- Packaging Frangible Articles (AREA)
- Die Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子を収納するチップトレーに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a chip tray for storing semiconductor devices.
従来、この種のチップトレーの構造は、第５図および第
６図に示す、平面図，断面図のようにチップトレー１′
上に複数個設けられている凹部５′の底部の形状は平滑
面である。更に外周部士手６′には切欠き部がないもの
となっている。Conventionally, the structure of this type of chip tray is as shown in the plan view and cross-sectional view shown in FIGS. 5 and 6.
The bottoms of the plurality of recesses 5' provided above are smooth. Furthermore, there is no notch in the outer peripheral part 6'.
チップトレーの材質は非導電性材料が一般的であり、且
つ色は、白糸のもの，青，黄，橙等が主流となっている
。The material of the chip tray is generally a non-conductive material, and the main colors are white, blue, yellow, orange, etc.
従来のチップトレーの構造では、凹部の底部が平滑面と
なっているため、半導体素子底面に対し密着しやすい、
そのため半導体素子の取出しが容易でない。また外周部
士手に切欠き部がないためチップトレー洗浄後に洗浄液
の残渣が発生し、清浄度維持が難しい。更にチップトレ
ーが導電性でないためにチップトレーに帯電し、静電気
に弱い半導体素子を破壊することになっている。色につ
いても白糸，青，黄，橙等のため、自動認識に於ける２
値画像が不鮮明となり、自動化が容易ではない。以上述
べたような各種の問題点があった。In the conventional chip tray structure, the bottom of the recess is a smooth surface, so it is easy to adhere to the bottom of the semiconductor element.
Therefore, it is not easy to take out the semiconductor element. Furthermore, since there is no notch on the outer periphery, cleaning fluid residue is generated after cleaning the chip tray, making it difficult to maintain cleanliness. Furthermore, since the chip tray is not electrically conductive, the chip tray is charged with electricity, which destroys semiconductor elements that are sensitive to static electricity. As for the colors, there are white threads, blue, yellow, orange, etc., so it is difficult to recognize 2 in automatic recognition.
The value image becomes unclear and automation is not easy. There were various problems as mentioned above.
本発明のチップトレーは半導体素子を収納する凹部の底
部に溝，凹部あるいは凸部を設けているため、半導体素
子底面との接触面積が小さくなり、密着しないようにな
っている。外周部士手４辺の各一辺には少くとも１カ所
の切欠き部を設けているため、チップトレー洗浄液が凹
部にたまることなく流れ出るため、洗浄液の残渣は残ら
ない。Since the chip tray of the present invention has a groove, a recess, or a convex portion at the bottom of the recess in which the semiconductor element is housed, the contact area with the bottom surface of the semiconductor element is small and the chip tray does not come into close contact with the bottom surface of the semiconductor element. Since at least one notch is provided on each of the four sides of the outer circumference, the chip tray cleaning liquid flows out without accumulating in the recesses, so that no cleaning liquid residue remains.
また材質は導電性材料を用いているため、帯電せずｉ？
ＩＴ＆気の強弱に関係なくあらゆる半導体素子を収納で
きる。更に色は黒色を用いているため、認識に於ける２
値化再像が鮮明となるため自動化が容易となる。またチ
ップトレーに導電性を持たせる方法として導電性塗布す
る手段もある。Also, since it is made of conductive material, it will not be charged.
It can store all kinds of semiconductor elements regardless of their IT and energy level. Furthermore, since black is used as the color, 2.
Automation is facilitated because the digitized reimage becomes clearer. There is also a method of applying conductive coating to the chip tray to make it conductive.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明一実施例の平面図であり、第２図は第ｌ
図のＡ−Ａ’断面図である。第３図は本発明の他の実施
例の平面図、第４図は第３図のＢ−Ｂ’断面図である。FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a plan view of one embodiment of the present invention.
It is an AA' cross-sectional view of the figure. FIG. 3 is a plan view of another embodiment of the present invention, and FIG. 4 is a sectional view taken along line BB' in FIG.
チップトレー１の材質には、半導体素子の静電気による
破壊防止のために導電性材料を、認識自動化のために黒
色のものを用いている。チップトレー清浄度維持のため
と洗浄性向上のために４辺ある外周部士手６の各ｌ辺に
少くとも１カ所の切欠部〜３を設けている。更に半導体
素子取出し容易化のために深さ０． １ ｍｍ〜ｌ．
Ｏ ｍｍ程度の溝２を十文字に配置している。尚、本構
造のチップトレーの製作は、戒型金型により容易に実施
できるものである。第３図，第４図の実施例では半導体
素子取出し容易化のために溝２の代りに、１．０’ｍｍ
〜２．０’ｍｍ程度の半球凸部を設けた例であるが、こ
れは溝や半球凸部のように凹部凸部どちらでもよく、効
果は全く同じである。また導電性を持たせるために黒色
のチップトレー全体に導電性塗料を塗布しても同じ効果
が得られる。The material of the chip tray 1 is a conductive material to prevent damage to semiconductor elements due to static electricity, and a black material is used for automatic recognition. In order to maintain the cleanliness of the chip tray and to improve the cleaning performance, at least one notch 3 is provided on each side of the outer peripheral part 6 having four sides. Furthermore, the depth is set to 0.0 mm to facilitate the extraction of semiconductor elements. 1 mm~l.
Grooves 2 of about 0 mm are arranged in a cross pattern. Incidentally, the chip tray having this structure can be easily manufactured using a molding die. In the embodiments shown in FIGS. 3 and 4, a groove of 1.0 mm is used instead of the groove 2 to facilitate taking out the semiconductor element.
Although this is an example in which a hemispherical convex portion of approximately 2.0 mm is provided, this may be either a concave portion or a convex portion, such as a groove or a hemispherical convex portion, and the effect will be exactly the same. The same effect can also be obtained by applying conductive paint to the entire black chip tray to make it conductive.
以上説明したように本発明は、利質を黒色にしたことに
よる自動認識の容易化，材質に導電性材料を用いたこと
，あるいは、導電性塗料の塗布による半導体素子の静電
気破壊防止２外周士手４辺の各１辺に少くとも１カ所以
上の切欠部を設けたことによる洗浄作業と清浄度維持の
容易化，凹部の底部に溝あるいは半球凸部等の凹，凸を
設けたことにより半導体素子の密着防止が計られ、取出
し容易化が可能になった。等の各種効果を有する。As explained above, the present invention facilitates automatic recognition by making the material black, uses a conductive material, or prevents electrostatic damage of semiconductor elements by applying conductive paint. Easier cleaning work and cleanliness maintenance by providing at least one notch on each of the four sides of the hand, and by providing grooves or concave or convex portions such as hemispherical protrusions at the bottom of the concave portion. This prevents the semiconductor elements from sticking together, making it easier to take them out. It has various effects such as.
第ｌ図は本発明の一実施例を示す平面図、第２図は第１
図のＡ−Ａ’断面図である。第３図は本発明の他の実施
例を示す平面図、第４図は第３図Ｂ−Ｅ’断面図である
。第５図は従来技術の平面図、第６図は第５図のＣ−Ｃ
’断面図である。
１，１′・・・・・・チップトレー ２・・・・・・溝
、３・・・・・・切欠部、４，４′・・・・・・半導体
素子、５，５′・・・・・・凹部、６，６′・・・・・
・外周部士手、７・・・・・・半球凸部。Fig. 1 is a plan view showing one embodiment of the present invention, and Fig. 2 is a plan view showing one embodiment of the present invention.
It is an AA' cross-sectional view of the figure. FIG. 3 is a plan view showing another embodiment of the present invention, and FIG. 4 is a sectional view taken along the line B-E' in FIG. Figure 5 is a plan view of the prior art, and Figure 6 is C-C in Figure 5.
'This is a cross-sectional view. 1, 1'... Chip tray 2... Groove, 3... Notch, 4, 4'... Semiconductor element, 5, 5'... ...Concavity, 6,6'...
・Outer peripheral part, 7... Hemispherical convex part.
Claims (1)
部を設けるとともに、凹部の外周土手部４辺の各１辺に
少くとも１ヵ所以上の切欠部を備え、チップトレー全体
に導電性塗料を塗布するか、あるいは、チップトレーの
材質に黒色導電性材料を用いたことを特徴とする半導体
素子用チップトレー。A groove, a recess, or a convex portion is provided at the bottom of the recess that accommodates the semiconductor element, and at least one notch is provided on each of the four sides of the outer peripheral bank of the recess, and the entire chip tray is coated with conductive paint. A chip tray for a semiconductor device, characterized in that the chip tray is coated with a black conductive material or a black conductive material is used as the material of the chip tray.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1310128A JP2540960B2 (en) | 1989-11-28 | 1989-11-28 | Chip tray for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1310128A JP2540960B2 (en) | 1989-11-28 | 1989-11-28 | Chip tray for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03169042A true JPH03169042A (en) | 1991-07-22 |
| JP2540960B2 JP2540960B2 (en) | 1996-10-09 |
Family
ID=18001510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1310128A Expired - Fee Related JP2540960B2 (en) | 1989-11-28 | 1989-11-28 | Chip tray for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2540960B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0528045U (en) * | 1991-09-17 | 1993-04-09 | 株式会社デイスコ | Base member for wafer mounting |
| WO2011036826A1 (en) * | 2009-09-28 | 2011-03-31 | シャープ株式会社 | Storage tray |
| CN114300368A (en) * | 2022-03-07 | 2022-04-08 | 成都先进功率半导体股份有限公司 | Method for welding scattered crystal grain chips by using welding piece equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5956736U (en) * | 1982-10-08 | 1984-04-13 | 日本電気株式会社 | Grooved tip tray |
| JPS62200586U (en) * | 1986-06-11 | 1987-12-21 | ||
| JPH01113466A (en) * | 1987-06-03 | 1989-05-02 | Jiyuraron Kogyo Kk | Antistatic synthetic resin molding dissipating static charge |
-
1989
- 1989-11-28 JP JP1310128A patent/JP2540960B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5956736U (en) * | 1982-10-08 | 1984-04-13 | 日本電気株式会社 | Grooved tip tray |
| JPS62200586U (en) * | 1986-06-11 | 1987-12-21 | ||
| JPH01113466A (en) * | 1987-06-03 | 1989-05-02 | Jiyuraron Kogyo Kk | Antistatic synthetic resin molding dissipating static charge |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0528045U (en) * | 1991-09-17 | 1993-04-09 | 株式会社デイスコ | Base member for wafer mounting |
| WO2011036826A1 (en) * | 2009-09-28 | 2011-03-31 | シャープ株式会社 | Storage tray |
| CN102470980A (en) * | 2009-09-28 | 2012-05-23 | 夏普株式会社 | storage tray |
| CN114300368A (en) * | 2022-03-07 | 2022-04-08 | 成都先进功率半导体股份有限公司 | Method for welding scattered crystal grain chips by using welding piece equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2540960B2 (en) | 1996-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |