JPH03169123A - Semiconductor circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog-to-digital converter, for example, a successive approximation type analog-to-digital converter (hereinafter referred to as abbreviated as "K") built in a semiconductor integrated circuit such as a microcomputer or a peripheral controller. (also referred to as A/D) converters.

[Prior art] The successive approximation type analog-to-digital converter (hereinafter also referred to as single KA/D converter) built into the data processing L8I, such as the Micro Combi Ichiyo, is a sampling circuit for analog signals and an analog-to-digital conversion circuit. Comparison data register and digital/analog (hereinafter also referred to as single KDlA) for generating a doji-ized level for
The OA/D conversion consists of a conversion circuit, a comparison circuit that compares the generated quantization level with the level of the sampled analog signal, and a control circuit that controls the operation of the plurality of circuits mentioned above. Although not particularly limited, the most significant bit of the comparison data register is initially set to "1", and the other bits S except for the most significant bit are initially set to rOJ. First, the quantization level corresponding to the most significant digit "1", that is, the voltage level half the full scale voltage, is applied from the D/A converter circuit to the comparator circuit. The comparison circuit compares this quantization level with the voltage level of the sampled analog signal to determine the magnitude relationship between them. If the comparison result is more than half of the 7 scale voltage, the most significant bit of the comparison data register is set to the 11 state of "1". If the comparison result is less than half of the full-scale voltage, the most significant bit of the comparison data register is set to “0”.
will be changed to

In the manner described above, the value of the most significant bit is determined.

In the comparison operation of the second bit, as in the determination operation of the most significant bit, [1] First, the lower bit of the most significant bit (hereinafter referred to as the second bit) of the comparison data register is set to "1". The quantization level corresponding to "1" of the second bit, that is, the voltage level of 1/4 of the full-scale voltage KR, the voltage level obtained by superimposing the load voltage (the voltage level of half the full-scale voltage) of the upper digit is the D/A Output from the converter to the comparator circuit. Then, the comparison circuit again compares the D/A conversion output and the voltage level of the analog signal. Depending on the result, the value of the second bit is determined to be "1" or "0". Thereafter, by successively repeating the same operation using the least significant bit 1, the voltage level of the sampled analog signal is converted into a corresponding digital signal and set as digital data in the comparison register.

As described above, since the successive approximation type A/D converter successively compares the voltage level of the input analog signal with the quantization level, the conversion operation requires a predetermined time.

That is, the conversion time of the successive approximation type A/Di converter is longer than the conversion time of the parallel comparison type A/D converter.

Therefore, when converting an analog signal into a digital signal using successive approximation type A/D conversion, highly accurate conversion cannot be performed unless the analog input signal maintains a constant level during the conversion period.

For this reason, an analog input signal with a sample and hold function is equipped with a hold circuit that stores the voltage level of the analog input signal that is sampled in a hold capacitor during the comparison operation period.
A Di converter is provided.

An example of a document describing a single-chip microcombinator with a built-in successive approximation type A/D converter with a sample/hold function is "Hitachi Original Single-chip Microcomputer" published by Hitachi, Ltd. in August 1988. H8/532 Overview-'IJ No. 26
There is a page.

[Problem to be solved by the invention]

The present inventor studied the sample and hold function of a successive approximation type A/D converter, particularly a successive approximation type A/D converter built into a semiconductor converter circuit. According to this, in order to improve the conversion efficiency, the voltage level of the analog input signal must be stably stored in the hold capacitor. To this end, it is necessary to substantially eliminate noise generated on the semiconductor substrate due to manufacturing variations in undesirable capacitance elements parasitic to stray capacitance switching elements in wiring to which analog signals are supplied, and potential fluctuations on the semiconductor substrate. Therefore, it is necessary to increase the hold capacitance to a negligible extent. However, if the hold capacitor is shortened, the charging time required to charge the voltage level of the analog signal on the hold capacitor increases.

If the charging time is not sufficient, the conversion accuracy will inevitably decrease. However, if the charging time is too long, the efficiency of the conversion operation will decrease and the level of the input analog signal, which fluctuates widely, will not be able to be accurately sampled. For this reason, the capacitance value of the hold capacitor of the successive approximation type A/D converter included in the semiconductor integrated circuit is such that the charging time is within a range where the charging time is not too long and the conversion ff is relatively high.
The size is set to hold honey. However, when converting an analog input signal with extremely large changes into digital, there is a risk that the analog input signal may fluctuate during the charging period of the hold capacitor, so the conversion accuracy may be lowered. The inventor discovered this.

1. Since the operation of the A/D converter built into a microcomputer is uniquely determined according to the operating clock frequency (system clock) that determines the entire operation cycle of the microcomputer, the hold The charging time of the analog input signal to the capacitor also depends on its operating clock frequency. Therefore, when the microcomputer is operated at a relatively low speed due to system operation, the time required to charge the analog input signal to the hold capacitor becomes relatively long. Therefore, when charging a hold capacitor with the voltage level of an analog input signal that has a large potential change, there is a risk that the conversion efficiency of the A/D transformer will decrease due to the change in the voltage level of the analog input signal during the charging period. It was revealed by the inventor's IttK that this phenomenon becomes even more remarkable.

Furthermore, an A/D converter without a hold function must sample an analog signal at each comparison step of each quantization level. Therefore, the accuracy of A/D conversion for analog input signals with large potential changes becomes extremely low.

Therefore, the present inventor considered providing an external high-performance sample hold circuit in order to improve the A/D conversion accuracy for analog signals with large potential changes. However, conventional A/D converters do not have an output means for outputting to the outside a sampling start timing signal, a sampling end timing signal, or a timing signal for notifying the sampling period of an analog signal.
It has been found that there is a problem in that even if an external KiA performance sample tts4-hold circuit is provided, the above timing cannot be given to the external sample-4 hold circuit. Additionally, the operating status of the A/D converter cannot be easily communicated to the source of the analog signal;
On the analog signal processing side, we have found that it is not possible to easily meet the requirements of controlling the analog signal generation source, for example, the external sample company's hold circuit, from a microcomputer.

SUMMARY OF THE INVENTION An object of the present invention is to provide an A/Di converter that can effectively utilize an externally buttoned sample/hold function. Another object of the present invention is to provide an A/D converter that can easily improve conversion accuracy depending on internal operating conditions, the state of an analog input signal, and the like. Still another object of the present invention is to provide an A/D converter that realizes controllability over an analog signal generation source. Still another object of the present invention is to provide a microcombination device incorporating an analog-to-digital converter having an external terminal for outputting analog signal sampling timing and the like to the outside of the chip.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, at least one of the strobe signals for notifying the start and end of sampling of an analog signal or the sampling period is sent to an analog-to-digital converter built in a semiconductor integrated circuit such as a single-chip microcomputer. Means for outputting to the outside via the external terminal of the semiconductor integrated circuit is provided.

[For production]

According to the above means, the strobe signal for notifying the outside of the sampling operation state of the analog signal is a high-performance sample number that should be provided externally in order to improve the A/D conversion accuracy for analog input signals with large potential changes. The high-performance sample and hold circuit recognizes the strobe signal as a sampling timing signal and is controlled to sample the analog signal. It is possible to effectively utilize the sample and hold function of the VC button, to improve the conversion accuracy according to the operating conditions of the analog-to-digital converter, and to improve the controllability of the analog signal generation source.

〔Example〕

FIG. 1 shows a single-chip microcomputer 5 incorporating a successive approximation type A/D converter 1, which is an embodiment of the present invention.
It shows.

Single-chip microcomputer 5 shown in the same figure
is formed on a single-crystal silicon semiconductor substrate indicated by a dashed line using a known CMOS process or bibolar CMOS process. Therefore, the illustrated microcomputer 5 has an N-channel type MO8FET and a P-channel type MOSFET, or an N-channel type MOSFET, a P-channel type MO8FET.
and an NPN type bibolar transistor.

The microcomputer 5 includes, in addition to the A/Di converter 1, a central processing unit (CPU) 2, a random access
Memory (RAM)3. Read-only memory (RO)
M) 30, built-in peripheral circuit 40, clock pulse generator CPG 50, digital I/O board 60, above CPU
Control circuit CPU for controlling the operation mode of 2.
CONT 70 and internal bus 4.

According to the program stored in the CPU 2fl, R, and OM 30, predetermined data processing described in the program is performed. For example, if the above program includes an analog signal data processing program, the above C
The PU instructs the A/D converter 1 to convert the analog input signal into a digital signal, and also instructs the A/D converter 1 to write the converted digital signal into, for example, RAMB via the internal bus 4. .

The built-in peripheral circuit 40 is not particularly controlled, but includes a timer TR41, a free running timer FRT42, and a serial communication interface 8C.
I43t-contains. The timer TR41 is used, for example, to output a pulse signal of an arbitrary duty ratio to the outside via the digital I/O port 60. The free running timer FRT42 is, for example,
To measure the pulse width of a digital signal input via the digital I/O boat 60 or the period of an external clock, or to output a signal with an arbitrary waveform to the outside via the I/O boat 60. used. The above serial
Communication, Inter 7 Eighth SCI431d
, is used to control the reception of serial data from the outside and the transmission of serial data to the outside. In this way, the illustrated microcomputer 5 has improved internal functions and can be applied to various data processing systems. In addition, the above-mentioned timer 41, free running timer FRT42 and serial communication 1
The interface SCI 43U is controlled by the central processing unit 2 via an internal bus to apply their operations to the data processing system to be handled. clock·
Pulse generator (GP) 50 is external terminal XT
, and XT, based on the oscillation frequency (2φ) of the crystal oscillator 80 connected between
10MHz), A/D converter operating clock φ/8(=
10 MHz/8)% and an operation clock (not shown) for the peripheral circuit 40. The CGP 50 has the crystal oscillator 80 icW connected therein to the CP
An oscillator that generates a clock signal 2φ with twice the frequency of the operating clock (system clock) φ of U2, which receives the clock 2φ and divides the frequency by 2 to generate a system clock,
A brancher that creates a clock φ, a clock that divides the system clock φ by 8, or an operation clock for the built-in peripheral circuit 40 (φ/2, φ/4, φ/8, φ16, etc.) Including brisket shaped like.

The digital I/O boat 60 is provided between the internal bus 4 and the external data terminals DTa to DTn, and inputs one or more digital data on the internal bus 4 to control the operation of the external peripheral device 90. Digital data from the external peripheral device 90 can be output to one or more specific external data terminals (DT) or to monitor the operating status of the external peripheral device 90. It is controlled to input to the internal bus from the terminal (DT). Furthermore, the digital I/O port 60 allocates one or more of the external terminals DT1 to DTn as a dedicated input, dedicated output, or dedicated output terminal for the built-in peripheral circuit 40, and It is controlled so that data can be transferred between the dedicated terminal and the peripheral circuit 40 via the dedicated bus 44. Control of the digital I/O port 60 can be executed by the CPU 2K according to a program stored in the ROM 30.

The control circuit CPU CONT70 is connected to the external peripheral device 9.
The operation of the CPU 2 is controlled by receiving control signals such as a reset signal, an interrupt request signal, a standby signal, and a mode setting signal from external terminals CTI to CTfm connected to the CPU 2.

The microcomputer 5 also has a 5-volt power supply voltage DVCC and an O-volt power supply voltage for digital circuits such as the CPU 2, RAM 3, ROM 30, built-in peripheral circuit 4Q, CPG 50, and digital I/O board 60. Power supply terminals 8T and 8T to which ground voltage pvss is supplied, and A/
Reference power supply voltage AVCC and ground potential A for D converter 1
It includes power supply terminals 8T3 and 8T4 to which Vss is supplied, respectively.

Furthermore, the external terminal to which the analog signal AiN should be supplied (
An external terminal (second terminal) ACT is provided to which a strobe signal 881 or 882 output from the first terminal (first terminal) AT and the A/D converter l is supplied. Above terminal ATF
i, output terminal 0 of external sample and hold circuit 20
is combined with

The control terminal C of the circuit 20 is coupled to the terminal ACTK to receive the strobe signal SS1 or 882. Further, the circuit 200 input terminal receives the original analog signal generated from the analog sensor 100. The external sample and hold circuit 20 receives the strobe signal SS1 or #'i input to its control terminal C.
sampling and holding the original analog signal from the sensor 100 in response to the high level of ss2;
Analog input signal Aint corresponding to the voltage level of the analog signal held from its output terminal 0 - terminal λT
Output to. The above analog sensor 100 has 4! Although not limited to hot wire sensors. This hot wire sensor is a type of air/7-low sensor, consisting of a first resistance element that generates heat and a second resistance element that has a constant resistance value and is connected in series between a power supply terminal (Vcc) and a ground terminal (GND). element. The first resistance element is
If there is a variable resistance element and the air flow rate is increased,
As the amount of heat generated decreases, its resistance value increases, and when the flow rate of air is small, the amount of heat generated increases, so the resistance value decreases. The analog output signal is
It is taken out from the connection point between the first resistance element and the second resistance element. As understood from the above, this analog output signal has five pressure levels divided by the first and second resistance elements K, and when the air flow rate changes rapidly, the potential change of the heavy pressure level also changes. It is violently done.

Note that the analog sensor is not limited to the hot wire sensor, but may also be a pressure sensor for detecting the same pressure in the cylinder of an engine installed in an automobile, for example. When the A/D converter 1 is not used, the external terminals AT and ACT are connected to the digital I/O terminals in order to effectively utilize the terminals AT and ACT.
Since it is connected to the /O boat 60, it can also be used as an input/output terminal for digital signals.

Further, when the terminal AT receives an analog signal, the impedance of the digital input/output circuit connected to the terminal ATK of the digital I/O port 60 is set high to prevent the level of the analog signal from changing.

The successive approximation mA/D converter IFi in FIG. 1 includes, but is not limited to, a sample and hold circuit 6 for analog signal A in, a comparison data register 7 for generating a quantization level for analog-to-digital conversion, and A D/A conversion circuit 8, a comparison circuit 9 that compares the quantization level with the voltage level of the sampled analog input signal, a data register 11 that holds the comparison result transferred from the comparison register 7, and an A/D conversion circuit. A control/status register 12 that holds control data instructing the start of operation of the A/D converter 1 and status data indicating the operating state of the A/D converter 1, its data register 1l, and the control/status register 12;
It includes a bus interface 13 that interfaces the status register 12 to the internal bus 4, and a control circuit 10 that controls the entire A/D converter 1. Incidentally, FIG. 2 shows the bit structure of the control/status register 12. ADF is a bit indicating the end of the conversion operation, AD
STFi is a bit that indicates the start of the conversion operation, AD E is a bit that indicates permission of an interrupt request due to the end of the conversion operation, and ES
H corresponds to a bit indicating the presence or absence of an external sample-and-hold circuit. Therefore, the above bits ADF, ADIT
, ADIE are storage circuits for storing the operating state of the A/D converter, and the bit E8H is considered a storage circuit for storing the external state of the microcomputer 5.

For example, when converting 8-bit digital data to analog, the D/A conversion circuit 8 connects 256 resistive elements of the same resistance value in series, and switches the switching elements in order from the connection node of each resistive element. It has an IJ ring circuit. By controlling the switching elements of the IJ circuit by the digital data given from the comparison data register 7, the D/A converter 8 outputs the quantization level '1irei' which is weighted according to the value of the digital data. generate.

This quantization level vref is supplied to a comparator circuit 9, which may be implemented by an operational amplifier.

The sample/hold circuit 6 has a sampling signal 8
The analog signal A remains on only during the assertion period of E.
a sampling switch 6A that inputs lfl;
A hold capacitor 6B that stores the voltage level of the analog signal AID supplied through this sampling switch 5Ai
including. The capacitance value of this hold capacitor 6A is approximately 8 pF. The sampling signal SE is supplied to the A/D converter 1
When the operation starts, it is asserted for a predetermined period prior to the successive approximation operation. The operation of the A/Di converter 1 is based on the A/D converter 1 of the control/status register 12.
The conversion start bit ADSTVc is started by writing data (for example, ``1'') from the central processing unit 2 instructing the start of the operation of the A/Di converter 1 to 1.

The control circuit 10 further responds to the A/D conversion start bit and AD8TK'''1'' being written to 1, and controls the N channel provided between the external terminal AT and the six sampling switches. Switch MO8FET 8W1t-
Generates an enable signal ADE for turning it on. Furthermore, if the control circuit 10 has data "1" set in bit ESH of the control status register 10, indicating that an external sample-and-hold circuit is provided, the strobe signal SS1 or 8S2 is set.
In order to supply gold to the external terminal ACTK, a strobe enable signal SSE is generated to turn on the N channel disabled switch MOSFETSW2.

As described above, the operations of the successive approximation type A/D converter 1 and the central processing unit 2 are synchronized with the operating clocks φ/8 and φ, respectively. Therefore, the conduction period of the six sampling switches corresponding to the assertion period of the sampling signal SE,
That is, the sampling time of the analog signal Ain is a predetermined number of cycles of the operation clock signal φ/8, for example, 63
It is considered a cycle. The predetermined number of cycles is such that a sufficient sampling time can be obtained in consideration of the capacitance value of the hold capacitor 6B. Actually, the predetermined number of cycles is fixedly determined in advance according to the logic of the control circuit 10. In other words, the operating clock φ
When is IOMHZ and the hold capacitance 6B is 8 pF, it is desirable that the sampling time is approximately (4 μs);
) is assumed to be 63 cycles.

The voltage of the analog signal stored in the hold capacitor 6B is supplied to the comparator circuit 9. The comparison circuit 9 compares the sampled voltage level with the quantization level Vref and supplies the result to the control circuit 10. The control circuit 10 corrects the relevant bit of the comparison data register 7 as necessary based on the comparison result, and moves on to control the next comparison operation. When the comparison operation from the most significant bit to the least significant bit is completed, the comparison data is transferred to data register 1.
1. Then, the A/Di conversion start bit AD8T of the control circuit ioVi control/status register l2 is cleared to ``0''.

The control circuit 10 controls the A/D conversion endbrag AD Fic of the control/status register 12.
Data ``'1'' indicating that A/D conversion has been completed
Write. Further, the control circuit 10 interrupts the A/D conversion when data indicating permission for an interrupt request due to completion of the A/D conversion operation is held in the interrupt enable bit }ADIE of the control/status register 12. An interrupt signal to notify the end of the operation is supplied to the central processing unit 2.

Thereby, the central processing unit 2 transfers the digital data held in the data register 11 to the module bus MB.
The successive approximation type A/D converter I of this embodiment controls the A/DK converter x and the bus interface 13't so as to take in the internal bus 4K via U8 and the bus interface l3. Sampling strobe signal 881 instructing the sampling start timing of the analog signal A 1 H by the sample hold circuit 6 or sampling strobe signal 882t indicating the sampling period - external terminal A from the control circuit 10
The data can be output to the outside of the microcomputer 5 via the CT.

FIG. 3 is an operational waveform diagram showing the operation of the microcomputer 50A/D converter l.

Hereinafter, the operation of the A/D converter 1 will be explained using the same figure. In the following, control/status register 1
The case where B,}ESH of 2 is set to 11'' by the CPU will be explained.

The CPU 2 executes data processing tl-in accordance with a predetermined data processing program stored in the ROM 30. If an analog data processing program exists in the data processing program, the CPU 2
A/ of control status register 12 in
In order to access the D conversion start bit ADST, an address signal Ai indicating the control status register 12 is generated in synchronization with the operation clock φ.

Further, the CPU 2 selectively sets the write signal to low level and sets the A/D conversion start bit ADST to "1" to indicate a write operation. The write cycle of the CPU 2 is executed in three periods of the operation clock φ, that is, in three states (three cycles).

The control circuit IO is configured to control the A/D conversion start, }A
In response to DST being set to 11'', an enable signal ADE and a strobe enable signal S8Ef are generated to turn on the switches !'dOSFET SW1 and SW2, and a high-performance external sample-and-hold circuit 20K sampling is generated. A pulse strobe signal 8:31 is generated to indicate the timing.The external sample-and-hold circuit 20 receives the strobe signal 88 supplied to the external terminal ACT via the source/drain bus of the switch MOSFET SW2.
1 at its control terminal C, and the analog signal supplied from the analog sensor 100 to its input terminal i is stored in its internal hold capacitor in synchronization with the high level of the strobe signal 881. That is, the external sample-and-hold circuit 20 sufficiently stores the voltage level of the analog signal in its hold capacitor during the period when the strobe signal 881 is at a high level. In other words, the sampling time of the high-performance external sample-and-hold circuit 20 is set to the time tSS when the strobe signal 8S1 is at a high level. Therefore, even if the analog signal output from the sensor 100 changes rapidly, the high level period tss of the strobe signal SSI is shortened, so that the analog signal from the seventh pin t-100 can be regarded as constant. can. Conversely, the external sample-and-hold circuit 20 has the performance to accurately store the voltage of the analog signal supplied to it even if its sampling time is shortened.

The control circuit 10 controls the strobe signal SSL SE
changes to high level for a predetermined period of time. During the high level period of the sampling signal SE, that is, the sampling time tsplO, the hold capacitor 6B transfers the voltage level of the analog signal, which does not change much, stored in the hold capacitor of the upper external sample and hold circuit 20 to the external terminal AT and the switch MOSFBT8W1. Noriichinu. It is fed through the drain path and stores it.

Thereafter, the A/D converter l converts the hold capacitor 6B to the hold capacitor 6B.
A sequence of comparison operations is performed to convert the voltage level stored within the voltage level into a corresponding multi-bit digital signal. Note that tholdH in the figure and the above-mentioned hold capacitor 6B indicate the hold time during which the voltage level of the analog signal is to be held.

Then, the control circuit 10 detects the end of the A/D conversion, clears the value of the A/D conversion start bit ADST in the control status register l2 from "1" to 11 0 n, and /D conversion end flag ADFt-'"O" or C)"1"K*y. The figure shows the conversion time required for tconvijl A/D conversions.

In addition, the above conversion time is assumed to be 13.4 μs〇And,
The above control circuit 10H, the above control status
Interrupt enable bit ADI of register 12
If E is set to ``1'', an interrupt signal is generated to the CPU 2.

Although the case where the strobe signal 88 1i is output has been described above, the strobe signal SS1 may be the strobe signal 882 shown in the figure. This strobe signal 882 is a signal that is set to a high level in synchronization with the rising edge of the sampling signal SE, and is set to a low level between the falling edge of the sampling signal 8E and the start of the comparison operation sequence. It is considered as a signal indicating the sampling period.

When converting the analog signal Ain, which has a large level change due to the nature of the signal, into a digital signal, the hold capacitor 6B is set at a sampling time uniquely determined by the configuration of the control circuit 10 and the frequency of the operating clock φ/8.
If the voltage of the analog signal Ain is charged to the voltage of the analog signal Ain, there is a risk that the level change of the input analog signal Ain that occurs during the charging period will affect the charging level and the A/D conversion accuracy will decrease. . Therefore, it is desirable to provide an external high-performance sample/hold circuit 20t and supply the analog signal A in to the successive approximation type A/D converter IK through this! Yes. In that case, the sample and hold circuit 2
0 needs to know the sampling timing of the sample-and-hold circuit 6 built into the A/D converter 1 of the microcomputer 5. According to the present invention, the sample/hold circuit 20 learns the sampling timing of the successive approximation type A/D converter l based on the rising edge change of the sampling strobe signal 8St or 882, and based on this, the sample/hold circuit 20 determines the sampling timing of the successive approximation type A/D converter l. - The hold circuit 2o also samples the analog signal in a short time and charges the sample and hold circuit 6 installed in the microcomputer 5K. Therefore, this sample and hold circuit 2
Since the charge level of 0 itself does not include the influence of the level change of the input analog signal, the sample-and-hold circuit 6 receives this, so that it is converted during the sampling period of the sample-and-hold circuit 6. Even if the level of the analog signal from sensor l00 changes, A/D conversion can be performed with high accuracy without being affected by the change.

1. In the above embodiment, the operating clock φ is set to 1oMH.
Although the sampling signal SE has been described as
Since the assertion period of , that is, the charging time of the analog signal A in to the hold capacitor 6B is also relatively long, the charge level to the hold capacitor 6B is the same as that of the analog signal A.
It becomes more susceptible to changes in the level of in. In such a case, as above, the sampling strobe signal 88
It is also effective to use the Fi882 to control the sample/hold circuit 20 provided outside the microcomputer 5. Although the above description has been made of the case where the analog signal from the sensor 100 changes sharply, the micro combinator 5 can also be applied to cases where the analog signal from the sensor 100 does not change sharply.

In this case, the external sampling and hold circuit 2
0Fi is not necessary, nor is it necessary to output the strobe signal 881 or 882. Therefore, if the pin E8H of the control status register l2 is set to ``0'', the signal SSE is not generated and the switch MOSFET SW2Fi is set to the OFF state. Therefore, the strobe signal 881 or FisS2 is connected to the external terminal ACT.
is not supplied.

FIG. 4 shows a successive approximation type A/D which is another embodiment of the present invention.
An i converter is shown. A successive approximation type A/D converter 2l shown in the figure has a sample circuit 22 instead of the sample and hold circuit 6 in the successive approximation type A/D converter 1 shown in FIG. Under the control of the control circuit 23, the A/D converter 2x executes a comparison operation sequence in which a comparison operation is sequentially performed every time the analog input signal Ain is sampled. Other arrangements are considered similar to the embodiment shown in FIG. That is, FIG. 4 is conceptually described.

The sampling strobe signal 883 instructing the first sampling start timing of the analog signal Ain by the successive approximation type A/D converter 21H and the sampling circuit 22 of this embodiment, or the period from the first sampling timing to the last sampling timing 1 The control circuit 23 outputs a sampling strobe signal 884 indicating a period that roughly corresponds to the microcomputer 5 to the outside of the microcomputer 5. As shown in FIG. 5, the sampling strobe signal S83 is not particularly limited;
Immediately after the A/D conversion start bit is enabled, it is asserted in the form of a pulse. In addition, the sampling strobe signal 884 is not limited to a value of 1, but corresponds between when the sampling signal SE' is asserted to compare the most significant bit and when the comparison operation of the least significant bit is performed. Assertion changes only during the period. Although both sampling strobe signals 883 and 884 may be outputted to the outside, in the embodiment shown in FIG. 4, one of them is outputted to the outside.

A/D without a hold function as shown in Figure 4
Since the converter 21 must sample the analog signal Ain at each comparison operation step of each quantization level, the converter 21 has to sample the analog signal Ain for each comparison operation step of each quantization level.
Conversion accuracy tends to be extremely low. At times like this,
Similar to the above embodiment, a sample hold circuit 24 is provided outside the micro combinator 5, and the sampling strobe signal SS3. SS4 is used to cause the sample and hold circuit 24 to hold the analog signal. The sample/hold circuit 24K is sampled for a certain period of time after the rising edge of the sampling strobe signals 883 and 884, for example, during the high level assertion period of the sampling strobe signal 883, and the sampling level Fi is sampled at the next assertion change 1 of the sampling strobe signal. The held voltage is then applied to the sampling circuit 22. Therefore, successive approximation type A/D
The converter 21 provides its operating state to the external sample and hold circuit 24 using sampling strobe signals 883 and 884, so that even if the successive approximation type A/D converter 21 itself does not have a hold function, it can be equipped with a sample and hold function. Similarly to the successive approximation type A/D converter 1, high conversion efficiency can be obtained for analog signals with large changes.

According to the above embodiment, the following effects can be obtained.

(1) The built-in hold capacitor f6B of the A/D converter included in the microcomputer substantially eliminates noise such as stray capacitance of wiring, parasitic capacitance of switch elements, manufacturing variations, and potential fluctuations of semiconductor substrates. Increasing the hold capacitance to a negligible extent and increasing the charging time for the hold capacitance may reduce the comparison operation efficiency or make it impossible to accurately sample input analog signal levels with large changes. From the viewpoint of preventing such problems, the size is set so that a relatively high conversion strength can be maintained without lengthening the charging time. Therefore, when converting an input analog signal with large changes into digital, the input analog signal fluctuates during the charging period of the hold capacitor and the conversion accuracy decreases! In cases where there is a risk of error, use successive approximation type A/D
The converter III-i outputs the sampling strobe signal 881 that instructs the start of the sampling timing and the sampling strobe signal ssz that indicates the sampling period to the outside of the microcombi Ichiyo 5. By providing a high-performance sample-and-hold circuit 20 that samples and holds the analog signal to be converted, the level of the analog signal to be converted does not change during the sampling period by the built-in sample-and-hold circuit 6. A/D conversion can be performed at a high n degree by reducing the influence of the change.

(2) In the case where the microcomputer 5 is operated at low speed in synchronization with the operating clock CLKK, which has a relatively low frequency, the assertion period of the sampling signal 8E, that is, the charging time of the analog signal Ain with respect to the hold capacitor 6B is also relative. The charging level of the hold capacitor 6B is easily influenced by the level change of the analog signal A j n, but in such cases, as in (1) above, the charging level of the hold capacitor 6B is
Using the SS2e, the sample and hold circuit 20 provided outside the microcomputer 5 can be charged with an analog signal level. As a result, even if the level of the analog signal to be converted changes during the sampling period by the built-in sample and hold circuit 6, A/D conversion can be performed with high accuracy without being affected by the change. can.

(3) The A/D converter 2l, which does not have a hold function, outputs an analog signal A at each comparison operation step of each quantization level.
Since it is necessary to sample i.sub.n, the A/D conversion accuracy for input analog signals with large changes is significantly lowered. However, since the successive approximation type A/D converter 21 can notify its operating state to the external sample and hold circuit 24 using the sampling strobe signals 883 and 8S4, the successive approximation type A/D converter 21
Even if the converter 21 itself does not have a hold function, high conversion accuracy can be obtained for analog signals with large changes, similar to the successive approximation type A/D converter 1 with a sample and hold function.

Although the invention made by the present inventor has been specifically explained based on examples, it is to be noted that the present invention is not limited thereto, and can be modified in various ways without departing from the gist of the invention. not.

For example, the D/A conversion circuit built into a successive approximation type A/D converter is not limited to the structure that incorporates the resistor string circuit described in the above embodiment, but also includes a ladder circuit that is weighted according to the quantization level. It is possible to change the structure to include a resistor network.

In addition, the resistor may be the on-resistance or off-resistance of a transistor, a polysilicon resistor, or the like, or may be an external resistor.

In addition, the sampling strobe signal is not limited to the above embodiment, and the assertion timing and assertion period of the signal can be freely changed as long as the signal can indicate the A/D conversion operation state to the outside.

For example, in the embodiment shown in FIG. 1, the sampling signal SE may be outputted to the outside as a sampling strobe signal.

The above explanation mainly describes the case where the invention made by the present inventor is applied to a successive approximation type A/Di converter built into a data processing LSI such as a microcomputer, which is the field of application in which the invention was made. However, the present invention is not limited thereto, and can also be applied to counting type A/D converters. The present invention provides at least A
It is applicable to conditions where the /D conversion state can be directly output to the outside of the chip.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this mVCsp is as follows.

That is, means is provided for outputting to the outside a strobe signal indicating at least one of the start and end of sampling of an analog signal, or the period thereof, using an analog-to-digital converter VC built into a semiconductor integrated circuit. treasure,
This has the effect of making it possible to effectively utilize an external sample/hold function. Further, there is an effect that conversion accuracy can be easily increased depending on internal operating conditions, the state of input analog signals, and the like. Furthermore, there is an effect that controllability over the analog signal generation source can be realized.

% when the operation of the analog-to-digital converter is synchronized to the operating clock of the central processing unit, or the charging time for the built-in hold capacitor to hold the voltage level of the input analog signal depends on the operating clock frequency above. Even if the A/D conversion accuracy is affected by the setting state of the operating clock frequency when doing so, the effect can be easily reduced.

[Brief explanation of the drawing]

Fig. fjgi is a block diagram of a single-chip microcomputer with a successive approximation type A/D converter that has a built-in sample and hold function, which is an embodiment of the present invention.
FIG. 3 is an explanatory diagram of the operation of the A/D converter shown in FIG. 1. FIG. 4 is a successive approximation type A without a built-in sample and hold function, which is another embodiment of the present invention. Block Diagram of A/D Converter FIG. 5 is an explanatory diagram of the operation of the A/D converter shown in FIG. l...Analog/digital (A/D) converter, 2
...Central processing unit (CPU), 3...Random access memory (RAM), 4...Internal bus, 5...
Single chip microcomputer.

Claims (1)

[Claims] 1. The semiconductor circuit device includes: a first external terminal to which an analog signal is to be supplied;
Conversion means for receiving an analog signal supplied to a terminal and converting the analog signal into a digital signal, the conversion means having a sampling circuit (6) for sampling the analog signal; coupled to the conversion means; , control means for controlling the operation of the conversion means, the control means selectively outputting a first control signal for operating the sampling circuit to the sampling circuit, and controlling the sampling circuit. A semiconductor circuit device comprising: outputting a second control signal based on the first control signal; and a second external terminal to which the second control signal is to be supplied. 2. The conversion means further includes means for generating a quantization level for analog-to-digital conversion, a comparison circuit for comparing the quantization level with the voltage level of the analog signal sampled by the sampling circuit, and 2. The semiconductor circuit device according to claim 1, further comprising a data register for holding conversion results. 3. The second control circuit includes a storage means (ESH) for identifying an external state of the semiconductor circuit device, and the control means refers to the storage means (ESH) to identify the external state of the semiconductor circuit device.
2. The semiconductor circuit device according to claim 1, wherein the semiconductor circuit device controls whether or not a control signal is supplied to the second external terminal. 4. The semiconductor circuit device according to claim 1, wherein the control signal includes a strobe signal for indicating at least one of the start, end, or period of sampling of the analog signal. 5. The semiconductor circuit device includes: a central processing unit (CPU) that performs predetermined data processing according to a predetermined operating clock; and clock generation means that supplies the predetermined operating clock;
2. The semiconductor circuit device according to claim 1, wherein said converting means performs analog-to-digital conversion in synchronization with said operating clock. 6. The semiconductor circuit device according to claim 1, wherein the sampling circuit includes a hold capacitor for holding the voltage level of the analog signal.