JPH0317192B2 - - Google Patents

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Publication number
JPH0317192B2
JPH0317192B2 JP56204076A JP20407681A JPH0317192B2 JP H0317192 B2 JPH0317192 B2 JP H0317192B2 JP 56204076 A JP56204076 A JP 56204076A JP 20407681 A JP20407681 A JP 20407681A JP H0317192 B2 JPH0317192 B2 JP H0317192B2
Authority
JP
Japan
Prior art keywords
electrode
film
layer
photoresist film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56204076A
Other languages
Japanese (ja)
Other versions
JPS58102975A (en
Inventor
Kenji Okamoto
Masayuki Wakitani
Kyotake Sato
Terunobu Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56204076A priority Critical patent/JPS58102975A/en
Publication of JPS58102975A publication Critical patent/JPS58102975A/en
Publication of JPH0317192B2 publication Critical patent/JPH0317192B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明はEL(エレクトロルミネツセンス以下
ELと称する)表示パネル等に好適な電極基板の
製造方法の改良に関するものである。
[Detailed description of the invention] (1) Technical field of the invention The present invention relates to EL (electroluminescence)
This invention relates to improvements in the manufacturing method of electrode substrates suitable for display panels (referred to as EL).

(2) 技術の背景 近年、EL層を誘電体層でサンドイツチ状に挾
んだ、いわゆる二重絶縁層構造の薄膜EL表示パ
ネルが開発、実用化されている。
(2) Background of the technology In recent years, thin-film EL display panels with a so-called double insulating layer structure, in which an EL layer is sandwiched between dielectric layers in a sandwich pattern, have been developed and put into practical use.

(3) 従来技術と問題点 このようなEL表示パネルの従来の製造方法に
ついて第1図を用いて説明する。まずガラスのよ
うな透明な絶縁基板1上に所定パターンの線状の
透明なインジウム錫酸化物(ITO)からなる下部
電極2を蒸着およびホトリソグラフイ法によつて
多数平行に配設する。次にこのような下部電極上
に酸化イツトリウム(Y2O3)のような第1の誘
電体膜3を蒸着によつて形成する。次にこの上に
マンガンを添加した硫化亜鉛(ZnS;Mn)より
なるEL層4を蒸着によつて形成する。更にこの
上にY2O3のような第2の誘電体膜5を蒸着によ
つて形成したのちこの上にアルミニウム(Al)
よりなる上部電極6を前記下部電極に対して直交
に配列するように蒸着およびホトリソグラフイ法
にて形成する。そして下部電極2と上部電極6と
の各交点部つまり対向領域で発光セルを構成し、
それら発光セルからの光を絶縁基板1側より観察
するようにしている。
(3) Prior Art and Problems The conventional manufacturing method of such an EL display panel will be explained with reference to FIG. First, a predetermined pattern of linear lower electrodes 2 made of transparent indium tin oxide (ITO) are arranged in parallel on a transparent insulating substrate 1 such as glass by vapor deposition and photolithography. Next, a first dielectric film 3 such as yttrium oxide (Y 2 O 3 ) is formed on such a lower electrode by vapor deposition. Next, an EL layer 4 made of zinc sulfide (ZnS; Mn) doped with manganese is formed thereon by vapor deposition. Further, a second dielectric film 5 such as Y 2 O 3 is formed on this by vapor deposition, and then aluminum (Al) is formed on this.
The upper electrode 6 is formed by vapor deposition and photolithography so as to be arranged perpendicularly to the lower electrode. A light emitting cell is formed at each intersection between the lower electrode 2 and the upper electrode 6, that is, the opposing region,
The light from these light emitting cells is observed from the insulating substrate 1 side.

ところで前述した誘電体膜3,5およびEL層
4のそれぞれの厚さは5000〓(オングストロー
ム)程度と極めて薄く、パターニングされた下部
電極上にこれら誘電体膜3,5、EL層4、上部
電極6を形成した状態を拡大した場合の断面図は
第2図のようになる。図で6は上部電極で下部電
極2との間に前述した誘電体膜3,5およびEL
層4が形成されているものとする。つまり下部電
極が所定のパターンに線状に形成されているの
で、その上に形成される誘電体膜3,5および
EL層4はその下部電極2に沿つた形で形成され、
該下部電極のエツジ部分A上に形成される上記誘
電体膜3,5およびEL層の厚さは、それ以外の
部分に形成されるものより薄く形成されるように
なる。
By the way, each of the dielectric films 3, 5 and the EL layer 4 described above has a very thin thickness of about 5000 Angstroms, and these dielectric films 3, 5, the EL layer 4, and the upper electrode are placed on the patterned lower electrode. An enlarged cross-sectional view of the state in which 6 is formed is shown in FIG. In the figure, 6 is the upper electrode, and between it and the lower electrode 2 are the dielectric films 3, 5 and EL.
It is assumed that layer 4 has been formed. In other words, since the lower electrode is formed linearly in a predetermined pattern, the dielectric films 3, 5 and
The EL layer 4 is formed along the lower electrode 2,
The dielectric films 3 and 5 and the EL layer formed on the edge portion A of the lower electrode are thinner than those formed on the other portions.

このような局部的に薄い誘電体膜を有するEL
表示パネルの上部電極と下部電極間に電圧を印加
してパネルを動作させた場合、前記局部的に薄い
誘電体膜が形成されている箇所に電界が集中し、
この部分で絶縁破壊を生じてパネルが劣化するお
それが生ずる。またこのような問題はEL表示パ
ネルの電極に限らず、外部電極形ガス放電表示パ
ネルのように多層膜構成を有する他の表示パネル
の電極基板においても同様に発生する問題であ
る。
EL with such locally thin dielectric film
When a voltage is applied between the upper electrode and the lower electrode of the display panel to operate the panel, an electric field is concentrated at the location where the locally thin dielectric film is formed,
There is a risk that dielectric breakdown will occur in this part and the panel will deteriorate. Further, such problems are not limited to electrodes of EL display panels, but also occur in electrode substrates of other display panels having a multilayer structure such as external electrode type gas discharge display panels.

(4) 発明の目的 本発明は上述した欠点を除去し、前述した電極
上に誘電体層が局部的に薄く形成されないように
し、その部分で電界の集中をなくした高信頼度の
表示パネル用電極基板を得ることを目的とするも
のである。
(4) Purpose of the Invention The present invention eliminates the above-mentioned drawbacks, prevents the formation of a locally thin dielectric layer on the electrode, and provides a highly reliable display panel in which the concentration of electric field is eliminated in those areas. The purpose is to obtain an electrode substrate.

(5) 発明の構成 かかる目的を達成するための本発明による電極
基板の製造方法は、絶縁基板上に電極となるべき
導電体層を形成したのち、該導電体層上に所定パ
ターンのホトレジスト膜を形成後、該パターニン
グせるホトレジスト膜をマスクとして導電体層を
エツチングして所定パターンの電極を形成し、そ
の後前記ホトレジスト膜面を含む基板上面に絶縁
膜を被着形成し、次いで前記ホトレジスト膜を除
去することにより当該レジスト膜上の絶縁膜も除
去してパターニングされた電極の間に絶縁膜を埋
設せしめるようにしたことを特徴とするものであ
る。
(5) Structure of the Invention A method for manufacturing an electrode substrate according to the present invention to achieve the above object is to form a conductor layer to become an electrode on an insulating substrate, and then apply a photoresist film in a predetermined pattern on the conductor layer. After forming the patterned photoresist film, the conductor layer is etched using the patterned photoresist film as a mask to form an electrode in a predetermined pattern, and then an insulating film is formed on the upper surface of the substrate including the photoresist film surface, and then the photoresist film is etched. By removing the resist film, the insulating film on the resist film is also removed, and the insulating film is buried between the patterned electrodes.

(6) 発明の実施例 以下図面を用いて本発明の一実施例につき詳細
に説明する。第3図より第7図までは本発明を
EL表示パネルに適用した場合の製造方法の工程
を示す断面図で第8図は本発明の方法によつて形
成したEL表示パネルの断面図である。
(6) Embodiment of the Invention An embodiment of the present invention will be described in detail below with reference to the drawings. The present invention is shown from Fig. 3 to Fig. 7.
FIG. 8 is a cross-sectional view showing the steps of the manufacturing method when applied to an EL display panel, and FIG. 8 is a cross-sectional view of an EL display panel formed by the method of the present invention.

まず第3図に示すようにガラス基板のような透
明な絶縁基板11上にITOよりなる透明な導電体
層12を蒸着によつて形成する。
First, as shown in FIG. 3, a transparent conductor layer 12 made of ITO is formed by vapor deposition on a transparent insulating substrate 11 such as a glass substrate.

その後該導電体層12上にホトレジスト膜を塗
布したのち、ホトリソグラフイ法により該ホトレ
ジスト膜を所定のパターンに形成する。第4図の
13はこのようにして形成したホトレジスト膜を
示す。
After that, a photoresist film is applied on the conductor layer 12, and then the photoresist film is formed into a predetermined pattern by photolithography. Reference numeral 13 in FIG. 4 shows the photoresist film thus formed.

その後第5図に示すように該パターニングした
ホトレジスト膜13をマスクとして下部の導電体
層を所定のパターンに塩酸(Hcl)等を用いてエ
ツチングして形成する。第5図の12Aはこのよ
うにして形成された所定パターンの下部電極であ
る。
Thereafter, as shown in FIG. 5, using the patterned photoresist film 13 as a mask, the lower conductive layer is etched into a predetermined pattern using hydrochloric acid (HCl) or the like. 12A in FIG. 5 is a lower electrode having a predetermined pattern formed in this way.

その後第6図に示すように該基板上全面に二酸
化シリコン(SiO2)膜14を蒸着によつて形成
し、前記パターニングして形成されている下部電
極12Aの間に埋設するようにする。次いでパタ
ーニングされて形成されているホトレジスト膜1
3をホトレジスト膜除去剤にて除去するとともに
いわゆるリフトオフ法によりその上のSiO2膜を
も除去する。この状態を第7図に示す。このよう
にすればパターニングされている線状の下部電極
12Aの間がSiO2の絶縁膜14にて埋設された
形となり下部電極と基板との間に段差の部分がな
くなる。
Thereafter, as shown in FIG. 6, a silicon dioxide (SiO 2 ) film 14 is formed on the entire surface of the substrate by vapor deposition, and is buried between the lower electrodes 12A formed by the patterning. The photoresist film 1 is then patterned and formed.
3 is removed using a photoresist film removing agent, and the SiO 2 film thereon is also removed by a so-called lift-off method. This state is shown in FIG. In this way, the space between the patterned linear lower electrodes 12A is buried with the SiO 2 insulating film 14, and there is no difference in level between the lower electrode and the substrate.

以上のように下部電極面と基板面との間に段差
を生じないようにしてから、その上にY2O3より
なる第1の誘電層15および(ZnS;Mn)より
なるEL層16、Y2O3よりなる第2の誘電層1
7、およびAlよりなる上部電極層18を順次蒸
着によつて形成したのち、該上部電極層18を所
定のパターンに下部電極と直交するようにホトリ
ソグラフイ法を用いて形成する。
After preventing a step from occurring between the lower electrode surface and the substrate surface as described above, the first dielectric layer 15 made of Y 2 O 3 and the EL layer 16 made of (ZnS; Mn) are placed thereon. Second dielectric layer 1 made of Y 2 O 3
7 and an upper electrode layer 18 made of Al are sequentially formed by vapor deposition, and then the upper electrode layer 18 is formed in a predetermined pattern so as to be orthogonal to the lower electrode using photolithography.

このようにすれば上部電極が平坦な状態で形成
され、従来の方法により形成したEL表示パネル
のような下部電極のエツジの部分で誘電体層が薄
く形成されて、その部分で絶縁破壊を生じるよう
な不都合を生じなくなる。
In this way, the upper electrode is formed in a flat state, and the dielectric layer is formed thinly at the edge of the lower electrode, such as in an EL display panel formed by the conventional method, causing dielectric breakdown at that part. Such inconveniences will no longer occur.

なお以上の実施例においては交流電圧で駆動す
る薄膜EL表示パネルに例を用いて述べたが、絶
縁基板の上に下部電極が形成されその上にEL層
および上部電極が誘電体膜を設けないで直接形成
されているような直流電圧で駆動するEL表示パ
ネルに対しても本発明は有益であり、その他ガス
放電表示パネル等の電極基板にも適用できる。ま
た下部電極を埋設するのはSiO2の他にY2O3のよ
うな絶縁膜でもよいし、また下部電極の表面より
高く突出して埋設してもよい。
In the above embodiments, a thin film EL display panel driven by AC voltage was used as an example, but the lower electrode is formed on an insulating substrate, and the EL layer and upper electrode are formed on the lower electrode without a dielectric film. The present invention is also useful for EL display panels driven by direct current voltage, such as those directly formed in the present invention, and can also be applied to electrode substrates such as gas discharge display panels. In addition to SiO 2 , the lower electrode may be buried with an insulating film such as Y 2 O 3 or may be buried so as to protrude higher than the surface of the lower electrode.

(7) 発明の効果 以上述べたように本発明の表示パネル用電極基
板の製造方法によれば電極上に積層される膜面に
段差を生じないので高信頼度の各種表示パネルが
得られる利点を生じる。
(7) Effects of the Invention As described above, according to the method of manufacturing an electrode substrate for a display panel of the present invention, there is no difference in level on the surface of the film laminated on the electrode, so there is an advantage that various highly reliable display panels can be obtained. occurs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の方法で製造したEL表示パネル
の断面図、第2図は従来の方法で形成したEL表
示パネルの不具合を示す図、第3図より第7図ま
では本発明をEL表示パネルに適用した場合の製
造方法の一実施例の工程を示す図、第8図は本発
明の方法により形成したEL表示パネルの断面図
である。 図において、1,11はガラス基板、12は電
極用導電体層、2,12Aは下部電極、3,5,
15,17は誘電体層、4,16はEL層、6,
18は上部電極、13はホトレジスト膜、14は
SiO2層、Aはエツジの部分を示す。
Figure 1 is a cross-sectional view of an EL display panel manufactured by the conventional method, Figure 2 is a diagram showing defects in the EL display panel manufactured by the conventional method, and Figures 3 to 7 show the EL display panel of the present invention. FIG. 8, which is a diagram showing the steps of an embodiment of the manufacturing method when applied to a panel, is a cross-sectional view of an EL display panel formed by the method of the present invention. In the figure, 1 and 11 are glass substrates, 12 is an electrode conductor layer, 2 and 12A are lower electrodes, 3, 5,
15, 17 are dielectric layers, 4, 16 are EL layers, 6,
18 is an upper electrode, 13 is a photoresist film, and 14 is an upper electrode.
SiO 2 layer, A indicates the edge part.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁基板上に電極となるべき導電体層を形成
したのち、該導電体層上に所定パターンのホトレ
ジスト膜を形成後、該パターニングせるホトレジ
スト膜をマスクとして導電体層をエツチングして
所定パターンの電極を形成し、その後前記ホトレ
ジスト膜面を含む基板上面に絶縁膜を被着形成
し、次いで前記ホトレジスト膜を除去することに
より当該レジスト膜上の絶縁膜も除去してパター
ニングされた電極の間に絶縁膜を埋設せしめるよ
うにしたことを特徴とする表示パネル用電極基板
の製造方法。
1 After forming a conductor layer to become an electrode on an insulating substrate, a photoresist film with a predetermined pattern is formed on the conductor layer, and then the conductor layer is etched using the photoresist film to be patterned as a mask to form a predetermined pattern. An electrode is formed, and then an insulating film is formed on the upper surface of the substrate including the photoresist film surface, and then the photoresist film is removed, thereby removing the insulating film on the resist film and forming a gap between the patterned electrodes. A method for manufacturing an electrode substrate for a display panel, characterized in that an insulating film is buried therein.
JP56204076A 1981-12-16 1981-12-16 Manufacture of display panel electrode substrate Granted JPS58102975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56204076A JPS58102975A (en) 1981-12-16 1981-12-16 Manufacture of display panel electrode substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56204076A JPS58102975A (en) 1981-12-16 1981-12-16 Manufacture of display panel electrode substrate

Publications (2)

Publication Number Publication Date
JPS58102975A JPS58102975A (en) 1983-06-18
JPH0317192B2 true JPH0317192B2 (en) 1991-03-07

Family

ID=16484370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56204076A Granted JPS58102975A (en) 1981-12-16 1981-12-16 Manufacture of display panel electrode substrate

Country Status (1)

Country Link
JP (1) JPS58102975A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6353892A (en) * 1986-08-22 1988-03-08 クラリオン株式会社 Electric field light emission device
JP2764591B2 (en) * 1988-12-16 1998-06-11 株式会社小松製作所 Thin film EL device and method of manufacturing the same
EP0907304B1 (en) * 1996-05-29 2002-11-06 Idemitsu Kosan Company Limited Organic el device

Also Published As

Publication number Publication date
JPS58102975A (en) 1983-06-18

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