JPH0317380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an MIS type large-scale integrated circuit using a master slice method.

Today, as large-scale integrated circuits become larger, there is a marked trend toward high-mix, low-volume production.In order to reduce manufacturing costs and shorten manufacturing time, large-scale integrated circuits are manufactured using the master slice method. Attention has been paid.

[Conventional technology]

The master slicing method is a method in which a large number of "basic element sets" (usually basic circuits from multiple transistors and resistors) are created in advance on a single semiconductor chip, and then interconnected according to the developed product. A large-scale integrated circuit having a desired electrical circuit operation is completed by creating a mask and connecting transistors and resistors.

According to the master slicing method, the basic element set consisting of transistors, resistors, etc. is formed in large quantities in advance, so when a request for product development arises, only the wiring mask needs to be made, which shortens the development period. be done. In addition, since the basic element set can be commonly used in various large-scale integrated circuits,
Development costs are also reduced.

In large-scale integrated circuits based on the master slice method, a set of basic elements such as transistors and resistors are generally arranged in a desired area of a semiconductor chip in an orderly matrix format. automatic placement and wiring processing can be effectively employed.

[Problem that the invention seeks to solve]

A master slice type large-scale integrated circuit is also divided into a basic element set including elements such as transistors and a wiring part, but it is extremely rare to use all the arranged transistors.
Therefore, when an unused basic element set exists, if the area above can be used as a wiring area, wiring will be considerably easier and the period for wiring design will be shortened.

The present invention was made in view of the various circumstances described above, and its purpose is to use complementary MIS transistors to have a simple structure, a small common area, and a transistor fabricated as a basic element set. An object of the present invention is to provide a master slice type semiconductor integrated circuit device in which the area above unused transistors can be used as a wiring area.

[Means for solving problems]

For this purpose, the semiconductor integrated circuit device of the present invention has a base semiconductor substrate on which a plurality of basic element assembly rows each consisting of a plurality of basic element sets are formed with a wiring area in between, and each of the basic element sets has a base semiconductor substrate. The element set is made up of a channel MIS transistor of one conductivity type and a channel MIS transistor of the opposite conductivity type arranged in parallel, and the gate electrodes of these MIS transistors are arranged such that their longitudinal direction is substantially orthogonal to the arrangement direction of the basic element set. placed in
A first power supply line having a terminal extraction part at an end thereof on the wiring region side, and passing over the gate electrode, source region, and drain region of the one conductivity type channel MIS transistor, and each of the opposite conductivity type channels.
A second power supply line passing over the gate electrode, source region, and drain region of the MIS transistor is located inside the terminal take-out portion, and extends along the arrangement direction of the basic element set to connect the basic elements. It is characterized by traversing the set row.

Examples will be described in detail below.

〔Example〕

FIG. 1 shows a basic element set (hereinafter referred to as basic cell) used to construct a large-scale integrated circuit according to the present invention. The basic cell includes two P-channel MIS transistors TR1 and TR2 and two N-channel MIS transistors TR3 and TR.
Consists of 4. Transistors on the same channel share either the source or the drain. In addition, two different pairs of transistors share a gate.

FIG. 2 shows a front view of an impurity-introduced region pattern and a gate electrode pattern that realize the circuit configuration of the basic cell shown in FIG. In the figure, 1 is a first gate electrode wiring layer made of, for example, polycrystalline silicon (Si), 1A, 1B, and 1C are terminal lead-out portions of the first gate, and 2 is a second gate electrode wiring layer also made of polysilicon. The gate electrode wiring layers 2A, 2B, and 2C are the second gate and the terminal lead-out portion. Also 3,
4 and 5 are N ⁺ type regions, which serve as source and drain regions of an N channel transistor. Further, 6, 7, and 8 are P ⁺ type regions, which become the source and drain regions of a P channel type transistor. Furthermore, 9 is an island-shaped P-type region (P-well) in which the N-channel transistor is formed, and is previously formed on the N-type silicon semiconductor substrate 10. Here, these source and drain regions can be formed by a conventional impurity introduction method, such as an ion implantation method or a solid phase-solid phase diffusion method from impurity-containing glass. Impurities are introduced into the gate electrode made of polysilicon at the same time as the source and drain regions are formed to impart conductivity.

As described above, the basic cell according to the present invention has three P ⁺ type and three N ⁺ type regions arranged symmetrically around the terminal extraction portions 1B and 2B of the gate electrode, and a space between the impurity introduced regions. Two vertically symmetrical gate electrodes are arranged covering each of the gate electrodes. In addition, terminal extraction portions of the electrodes of each gate are provided at both ends and in the center, and a gap is provided between the upper and lower gate electrodes to allow the terminals to be extracted from the impurity-introduced regions 4 and 7. In addition, FIG. 3 is a cross-sectional view taken along line A-A' in FIG. 2, and FIG. 4 is a cross-sectional view taken along line A-A' in FIG.
It is a cross-sectional view taken along the line B′, and in the same figure,
11 is a gate insulating film made of silicon dioxide (SiO ₂ ), for example, and 12 is a field insulating film similarly made of silicon dioxide.

The basic cells as described above are arranged in rows as a so-called array on one semiconductor chip. Here, if the basic cells are arranged in the vertical direction, a horizontal wiring area is secured for each basic cell. FIG. 5 shows the arrangement of basic cells on a semiconductor chip, and shows the arrangement area 2 of the basic cells.
Tens to hundreds of basic cells 21 are arranged in the vertical direction in each cell 0, and about 10 to 30 wirings are provided in the vertical wiring vacant area 22 provided between each array area 20. The array regions 20 can be arranged in dozens of rows laterally on the semiconductor chip as required. FIG. 6 is an enlarged plan view showing the arrangement of the basic cells 21, in which a horizontal empty area 23 for wiring is formed between the basic cells 21.
In this part, a gap is provided to accommodate about 1 to 4 wiring lines.

In this way, the horizontal wiring vacant area 23 exists between each basic cell, thereby making it possible to distribute the wiring in the horizontal direction. Local concentration of wiring reduces wiring efficiency, and dispersing wiring throughout a large-scale integrated circuit is important for improving wiring efficiency.

Further, as described above, since the gate electrode terminals of the basic cells are led out symmetrically into the vertical wiring vacant area 22, wiring is extremely easy and the degree of freedom in wiring can be increased. That is, even if the vertical wiring area 22 on one side becomes overcrowded, the vertical wiring process can be performed in the adjacent vertical wiring area using the terminals on the opposite side.

In realizing such vertical wiring and horizontal wiring, two wiring layers, one vertical and one horizontal, are used as wiring layers. Here, if the wiring layer closer to the semiconductor substrate, that is, the lower layer, is the first layer, and the wiring layer that is farther away, that is, the upper layer, is the second layer, then the first layer is in the direction of arrow A in FIGS. 5 and 6, that is, the basic It is parallel to the vertical direction in which the cells are arranged adjacently, and the second
The layers can be set in the direction of arrow B, that is, in the horizontal direction orthogonal to the first layer. The lower wiring layer is formed on a first insulating layer made of, for example, phosphorus silicate glass (PSG) that covers the polysilicon gate electrode, and the upper wiring layer is formed on an insulating layer also made of phosphorus silicate glass that covers the lower wiring layer. is formed. Furthermore, a phosphorus silicate glass layer for passivation is formed to cover the upper wiring layer.

Here, the first layer wiring is not only provided in the wiring vacant area 22, but also utilized on the basic cell array area 20, as shown in FIG. The wiring arranged on this basic cell is applied to the power supply line, and these are connected to the P ⁺ type region 24 provided on the island region 9 of the wiring vacant region 23 between the basic cells,
A resistive (ohmic) contact is made between the N ⁺ type region 25 on the N type silicon semiconductor substrate and the point marked with an x.

In complementary MIS circuits, unused input gates are not allowed to be unconnected.
Must be connected to the power line.

In order to process such empty input terminals, the horizontal wiring empty area 23 that exists in each basic cell described above is used.

In Figure 7, terminal outlet A and B or
If A' and B' are empty terminals, terminal outlet A
Alternatively, connect A' to the N ⁺ type region 25 using the first wiring layer, and connect terminal outlet B or B' to the P ⁺ region 24 using the first wiring layer. This allows the empty terminal to be easily connected to either the V _AA power supply or the V _SS power supply.

Processing of such empty terminals can be realized by connection processing using the empty area of the first layer sandwiched between the wiring provided in the vertical wiring empty area 22 and the power line. Vacant terminals can be processed regardless of the direction of the second wiring layer, and the wiring area on the semiconductor chip can be used very effectively.

On the other hand, in the master slice method, various gate circuits, flips, and
By using the basic elements used in the present invention, that is, basic cells, which must be able to form flop circuits, etc., dozens of types of logic gates, etc. can be created by appropriately connecting only between these basic cells.
A flip-flop circuit can be formed.

Next, an example of configuring a logical NAND circuit (NAND) using the basic cell according to the present invention will be shown.

Figure 8 is a logical symbol diagram of a NAND circuit, Figure 9
The diagram consists of complementary MIS semiconductor devices
It is a circuit diagram of a NAND circuit. FIG. 10 is a layout diagram of such a NAND circuit constructed using basic cells according to the present invention. 10th
In the figure, the thick solid lines are the first-layer wiring, the thin solid lines are the second-layer wiring, and the x marks indicate the points where each wiring is in ohmic contact with the impurity-introduced region in the semiconductor substrate through the electrode window. Yes, the * mark is the connection point between the first layer wiring and the second layer wiring. The connection point is provided by a through hole (Via), not shown, provided in an interlayer insulating layer made of, for example, phosphorous silicate glass (PSG). What should be noted here is that the
In the NAND circuit, the gap provided between the two gate electrodes 1 and 2 allows the NAND
The point is that the output of the circuit can be led to the vertical wiring regions on both sides of the basic cell.

FIG. 11 is a logical symbol diagram of a D-type flip-flop circuit, and FIG. 12 is a circuit diagram of a flip-flop circuit composed of complementary MIS semiconductor devices. FIG. 13 is a layout diagram of such a flip-flop circuit constructed using basic cells according to the present invention. In Figure 13, the thick solid line is the first layer wiring, and the thin solid line is the second layer wiring.
In the wiring layer, the x mark indicates that the wiring layer is in ohmic contact with the impurity-introduced region in the semiconductor substrate through the electrode window, and the mark indicates that the first layer wiring and the second layer wiring penetrate through each other. The point is that it is connected through a hole. In the configuration of this D-type flip-flop circuit as well, the output Q,
Q can be led to vertical wiring regions on both sides of the basic cell array.

In this way, one or more basic cells according to the present invention can be used to create flip-flop circuits.
If a NAND circuit can be formed, most logic configurations can be realized by combining these circuits, and this means that the basic cell according to the present invention has sufficient performance as a basic cell of the master slice method. and shows that it is excellent.

Further, by adopting the basic cell arrangement method according to the present invention, functional circuits can be effectively embedded without creating gaps between basic cells as long as wiring is permitted. That is, compared to the conventional master slice type large-scale integrated circuit, the semiconductor chip surface can be used more effectively, and the degree of integration of the large-scale integrated circuit can be further improved.

FIG. 14 shows an example in which a functional circuit configured by a combination of the basic cells is arranged in the basic cell array area 20. In the figure, 31 is a 3-input NAND circuit formation area, and 32 is a flip-flop.・Flop circuit formation area, 33 is an inverter formation area,
34 is a 2-input NR circuit forming area, 35 is a flip-flop circuit forming area, and 36 is a 2-input NR circuit forming area.
The NAND circuit forming area 37 is a 3-input NR circuit forming area. These circuits are appropriately connected using vertical wiring and horizontal wiring to construct a desired large-scale integrated circuit.

FIG. 15 is a schematic diagram of the surface of a large-scale circuit semiconductor chip in which the present invention is implemented, and in the figure, reference numeral 41 indicates an area where an interface circuit with the outside of the large-scale integrated circuit is formed and an area where input/output electrode pads are formed. .

That is, as shown in FIG. 16, an input/output (I/O) macros 44 consisting of an element arrangement section 42 in which a plurality of transistors and resistors are arranged and an input/output electrode pad 43 is provided. The I/O macro is an input/output buffer circuit (3-state output input buffer, 3-state output input buffer, true-output buffer, 3-state output input buffer, true output buffer, It has enough transistors and resistors to form a power input buffer, torque input buffer, etc.). Then, if necessary, a desired buffer circuit is provided by wiring I/O macros. Note that each of the input/output electrode pads 45 can be connected to an external circuit by connecting a general thin lead wire.

Note that, as described above, in each basic cell arrangement region 20, power supply lines V _SS and V _DD are provided in the vertical direction, but these power lines are much longer than other wiring lines. Therefore, a voltage drop occurs due to the resistance of the wiring itself, and the power supply voltage applied to a certain basic cell may differ depending on the location. Therefore, in the present invention, a voltage equalizing line 42' is provided in the horizontal direction for every 10 basic cells, for example, to equalize the voltages in the V _SS power line and the V _DD power line in each part on the semiconductor chip. This voltage equalization line is formed in the empty area of the second wiring layer.

In the embodiment of the present invention, the gate electrode of the MIS transistor constituting the basic cell is
The polysilicon gate is made of polycrystalline silicon, and conductivity is imparted to the polysilicon gate when forming the source and drain regions.

Use such polysilicon as a gate electrode
When forming an MIS type transistor, since the polysilicon layer has a relatively high resistance, it is difficult to increase the operation speed of the MIS type transistor.

Therefore, in an advanced embodiment of the present invention, when forming the wiring layer structure, a metal layer is formed on the polysilicon gate electrode on the same plane and parallel to the lateral wiring layer. , the metal layer and the polysilicon gate electrode are connected at the terminal lead-out portion of the polysilicon gate electrode, thereby substantially increasing the effective cross-sectional area of the polysilicon gate electrode and lowering the resistance of the polysilicon gate electrode.

The metal layer may have the same pattern shape as the polysilicon gate electrode located therebelow with an insulating film interposed therebetween, and may have a structure in which it is weighted with the polysilicon gate electrode. However, if the metal layer is in close proximity to horizontal wiring led out from regions 4, 7, etc., and there is a risk of problems occurring in the manufacturing process or electrical characteristics, as shown in FIG. The terminal lead-out portions of the silicon gate electrodes are connected in a straight line.

In the figure, 51 and 52 are metal layers, 53A,
53B, 53C and 54A, 54B, 54C
is a connection hole provided above the metal layers 51, 52 and the terminal extraction portion of the polysilicon gate electrode,
The other parts are given the same numbers as the parts shown in FIGS. 2 to 4, FIG. 6, FIG. 7, FIG. 10, etc. described above. Note that in addition to this, the gate electrode can also be formed of a highly heat-resistant metal.

〔Effect of the invention〕

As explained in detail above, the large-scale integrated circuit according to the present invention has a structure of a basic cell serving as a basic unit cell having a complementary MIS structure and is very small. It can accommodate a large number of basic cells. Furthermore, the degree of integration can be increased compared to conventional large-scale integrated circuits, and since the basic cell wiring structure consists only of gate electrode wiring without using a complicated wiring structure, it is extremely small. be. Therefore, it is not necessary to form a wiring layer exclusively for the basic cell on the basic cell, so that the basic cell can be used as a wiring area with or between other basic cells. Moreover, since the top of an unused basic cell can also be used as a wiring area between other basic cells, the degree of freedom in design is extremely high.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a common part constituting a large-scale integrated circuit according to the present invention, Fig. 2 is a front view of a pattern of the common part, and Fig. 3 is a cut along line A-A' in Fig. 2. 4 is a sectional view taken along line B-B' in FIG. 2, FIG. 5 is a plan view showing the arrangement of common parts on the chip, and FIGS. Figure 8 is a plan view showing the enlarged array.
Logic symbol diagram of NAND circuit, Figure 9 is NAND
The circuit diagram, Figure 10, uses common parts.
A layout diagram of a NAND circuit; Figure 11 is a logic symbol diagram of a D-type flip-flop circuit;
The figure is a circuit diagram of a flip-flop circuit, Figure 13 is a layout diagram of a flip-flop circuit, and Figure 1 is a circuit diagram of a flip-flop circuit.
FIG. 4 is a layout diagram showing an example of arranging functional circuits in a common partial array area, FIGS. 15 and 16 are overall schematic diagrams of a large-scale integrated circuit step embodying the present invention, and FIG. FIG. 7 is a plan view showing another embodiment of the basic element set in the invention. In the figure, 1 is the first gate electrode wiring layer, 1A, 1
B, 1C are terminal outlet ports, 2 is the second gate electrode wiring layer, 2A, 2B, 2C are terminal outlet ports, 3, 4,
5 is N ⁺ type region, 6, 7, 8 are P ⁺ type region, 9 is P
A mold island region, 10 is a semiconductor substrate, 11 is a gate insulating film, 20 is a basic cell arrangement area, 21 is a basic element set (basic cell), 22 is an empty area for vertical wiring,
23 is an empty area for horizontal wiring, 24 is a P ⁺ type area,
25 is an N ⁺ type region, 42' is a pressure equalizing line, and 51 and 52 are metal layers.

Claims (1)

[Claims] 1. A semiconductor substrate having a base semiconductor substrate in which a plurality of basic element set rows formed by arranging a plurality of basic element sets are formed with a wiring area in between, and each of the basic element sets has one conductivity type channel. An MIS transistor and a channel MIS transistor of opposite conductivity type are arranged in parallel, and the gate electrodes of these MIS transistors are arranged so that the longitudinal direction thereof is oriented in a direction substantially perpendicular to the arrangement direction of the basic element set,
A first power supply line having a terminal extraction part at an end thereof on the wiring region side, and passing over the gate electrode, source region, and drain region of the one conductivity type channel MIS transistor, and each of the opposite conductivity type channels.
A second power supply line passing over the gate electrode, source region, and drain region of the MIS transistor is located inside the terminal take-out portion, and extends along the arrangement direction of the basic element set to connect the basic elements. A master-slice type semiconductor integrated circuit device characterized by vertically traversing assembly rows. 2 The one conductivity type channel MIS transistor is P
The channel MIS transistor is a channel MIS transistor, the opposite conductivity type channel MIS transistor is an N-channel MIS transistor, the first power line is a high potential side power line, and the second power line is a low potential side power line. A master slice type semiconductor integrated circuit device according to claim 1, characterized in that: 3. It has a base semiconductor substrate in which a plurality of basic element set rows formed by arranging a plurality of basic element sets are formed with a wiring area in between, and each of the basic element sets is of one conductivity type channel MIS transistor and the opposite conductivity type. channel MIS transistors are arranged in parallel, and the gate electrodes of these MIS transistors are arranged such that their longitudinal direction faces in a direction substantially perpendicular to the arrangement direction of the basic element set,
A first power supply line having a terminal extraction part at an end thereof on the wiring region side, and passing over the gate electrode, source region, and drain region of the one conductivity type channel MIS transistor, and each of the opposite conductivity type channels.
A second power supply line passing over the gate electrode, source region, and drain region of the MIS transistor is located inside the terminal take-out portion, and extends along the arrangement direction of the basic element set to connect the basic elements. The first power supply lines or the plurality of second power supply lines are connected to each other by an equalizing line that cuts through the array and extends in a direction substantially perpendicular to the basic element assembly array. A master slice type semiconductor integrated circuit device characterized by the following.