JPH0317481Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit, and more particularly to a circuit for generating clock pulses synchronized with an input signal.

A digital audio disk is a device in which audio signals are digitized and optically recorded at high density on the surface of the disk at a constant linear velocity.The signal format recorded on the disk is determined, for example, as shown in Figure 1. It is being That is, in this system, one frame is made up of a fixed number of bits (for example, 588 bits), and these frames are consecutively recorded on the same disk at a constant linear velocity. The signal format of each frame is divided into a synchronization part PA and an information part PB, and the synchronization part PA is located at the beginning of each frame. Furthermore, the synchronizing part PA is composed of 22 bits as shown in Fig. 1, and when the first 11 bits are consecutively "0", the following 11 bits are consecutively "1", and so on. It is set so that when the first 11 bits are consecutively "1", the following 11 bits are consecutively "0". In this case, the first 11 bits are set to be the opposite of the last bit of the previous frame.
In this way, the format in which "0" or "1" are consecutively set in a predetermined unit bit (11 bits) is limited to this synchronization part PA in one frame. That is, the information section PB is configured so that a format in which 11-bit units of "0" or "1" are consecutive does not occur under any circumstances. In addition, in order to prevent the information section PB from converting to direct current when there is no signal, the signal is always a continuous "1" signal or "0" signal over 3 bits or more. Therefore, the information section PB is 3
It will be expressed as a continuous signal only over the range of ≦B<11 bits.

With a digital audio disk constructed in this manner, a high-fidelity audio signal can be easily obtained by optically reading and demodulating digital information on the disk at a constant linear velocity.

In this case, when demodulating the read signal, a clock pulse that matches the bit period during recording on the digital audio disk is generated, and each bit signal is discriminated by sampling the read signal using this clock pulse. The clock pulse in this case must be accurately synchronized with the digital audio disk read signal.

However, when reproducing audio discs, there is a problem that reading with a constant linear velocity cannot be performed due to uneven rotation of the motor or distortion of the disc, and the internal clock pulse of the readout signal becomes out of synchronization, making it impossible to perform high-precision reproduction. have.

Therefore, an object of the present invention is to provide a clock pulse generation circuit that can easily and reliably generate clock pulses synchronized with an external input signal, and can also reliably follow even relatively large phase shifts. That's true.

FIG. 2 is a circuit diagram showing an embodiment of the synchronizing signal generating circuit according to the present invention, which is particularly applied to the case of generating clock pulses synchronized with the reproduced signal of a digital audio disk. In the figure, 1 is a negative component cut circuit for extracting only the positive component of the reproduced signal A, and is composed of a resistor 1a and a diode 1b. Reference numeral 2 denotes a differentiating circuit for differentiating the output B of the negative component cut circuit 1, and as is well known, it is composed of a capacitor 2a, an operational amplifier 2b, and a resistor 2c. 3 cuts the negative component of the differential output C sent from the differentiating circuit 2 and outputs only the positive component as an output signal D.
This is a circuit for cutting off the negative components generated as a result of the oscillation, and is composed of a resistor 3a and a diode 3b. 4 is an output D which takes as input the differential output of the positive component supplied from the negative component cut circuit 3, and gives it a relatively gentle slope by rounding the trailing edge side.
between a diode 4a that bypasses the resistor 3b provided in the negative component cut circuit 3 only in the forward direction, and the output terminal of the negative component cut circuit 3, the power supply, and the case. A capacitor 4b and a resistor 4c are respectively connected to the capacitor 4b and the resistor 4c. A pull-up circuit 5 generates an output E by pulling up the output C of the differentiating circuit 2 by +5V, and is composed of a resistor 5a and a pull-up resistor 5b. 6
is formed by a D-type dual flip-flop circuit that individually latches the output D' of the slope shaping circuit 4 and the output E of the pull-up circuit 5 by a clock pulse CP supplied from a voltage-controlled variable oscillator 9, which will be described later. latch circuit, 7
is a differential circuit that obtains the difference between output signals F and G of the latch circuit 6, and is operated by using the output signal G as an inverting input via a resistor 7a and the output signal F as a non-inverting input via a resistor 7b. Amplifier 7c and
It is composed of a resistor 7d that feeds back the output signal of the operational amplifier 7c to the inverting input terminal, and a resistor 7e connected between the non-inverting input terminal of the operational amplifier 7c and ground. Reference numeral 8 denotes an active low-pass filter that receives the output signal H of the differential circuit 7 and sends out only the low-frequency component as the output signal I. As is well known, the filter 8 is configured by a resistor 8a, an operational amplifier 8b, and a capacitor 8c. It is configured. Reference numeral 9 is the voltage-controlled variable oscillator mentioned above, which connects the output signal I of the active low-pass filter 8 to a bus cap diode 9a.
The oscillation frequency can be varied by supplying the capacitance component to the capacitance component. The thus oscillated output is frequency-divided by a frequency divider 9b and then output as a clock pulse CP.
In this case, the voltage-controlled variable oscillator 9 oscillates at the reference frequency in the normal state, and is finely tuned by the output signal I of the active low-pass filter 8.

In the clock pulse generation circuit constructed in this manner, the voltage controlled variable oscillator 9 oscillates a clock pulse CP having a reference period, as shown in FIG. 3a. In this state, for example, Fig. 3b
When the reproduced signal A synchronized with the clock pulse CP is supplied to the negative component cut circuit 1 as shown in FIG. The output is as follows. Therefore, the output signal B in this case has its rising start portion synchronized with the rising edge of the clock pulse CP, as shown in FIG. 3c.
Then, the output signal B of this negative component cut circuit 1
is differentiated in the differentiating circuit 2, and an output signal C shown in FIG. 3d is obtained. The differential output signal C generated in this manner has its negative components cut off in a negative component cut circuit 3, and only its positive components are taken out. The positive polarity differential output D generated from this negative component cut circuit 3 is supplied to the slope shaping circuit 4, but the positive polarity portion of the differential output C generated from the differentiation circuit 2 is connected to a diode. 4a. Therefore, the output signal D' sent out from the slope shaping circuit 4 is as shown in FIG. 3e and as shown in FIG. 3d.
An output that rises along the rising edge of the differential output signal C shown in FIG. After this differential output signal C reaches its peak, the charging current of the capacitor 4b flows through the resistor 4c, so that the falling portion of the differential output signal C reaches the peak of the capacitor 4b.
The slope is gradually extended in accordance with the time constant determined by the value of b and the resistance 4c. That is, by passing the positive differential output through the slope shaping circuit 4, a gentle slope is imparted to the falling portion as shown in FIG. 3e.

On the other hand, the output signal C of the differentiating circuit 2 is biased with +5V in the pull-up circuit 5, so that the output signal E shown in FIG. 3f is outputted.

The output signals D' and E generated in this way are
At the rising edge of the clock pulse CP, the output signals D' and E are taken into the latch circuit 6 and held, respectively. 0" and "H" is called "1"), the outputs F and G of the latch circuit 6 are as shown in FIG.
The "0" state will continue as shown in h.
As a result, the output signal H of the differential circuit 7 which inputs the output signals F and G of the latch circuit 6 becomes "0" as shown in FIG. The generated output signal I
becomes the reference value Vr as shown in FIG. 3j. Therefore, the voltage-controlled variable oscillator 9, which receives the output signal I of the reference value Vr as a control input, generates a clock pulse.
Leave the CP oscillation frequency at the standard value.

Next, if the reproduced signal A is delayed in phase with respect to the clock pulse CP for some reason as shown in FIG. 4, the reproduced signal A will be delayed as shown in FIG.
At the falling edge of the clock pulse CP, the "0" level output signal D' outputted from the slave shaping circuit 3 and the "0" level output signal E outputted from the pull-up circuit 5 are taken into the latch circuit 6 at the rising edge of the clock pulse CP. As a result, the output F of the latch circuit 6 continues to be in the "0" state as shown in FIG. 4g, and the output signal G of the latch circuit 6 changes to the clock pulse CP as shown in FIG. It becomes "1" during one period of . As a result, the output signal H of the differential circuit 7 becomes "-1" only during the "1" period of the latch output G, as shown in FIG. 4i. In this way, at each falling edge of the reproduced signal A, the clock pulse
The output signal H of the differential circuit 7, which has a negative polarity only during one period of CP, is taken out via the low-pass filter 8, so that the output signal I becomes the reproduced signal A as shown in FIG. When Vr falls, the signal becomes lower than the reference value Vr. Therefore, the average value of this output signal I becomes a signal that is slightly lower than the reference value Vr, as shown by the dotted line in FIG. Positioning for the reproduced signal A is performed.

Next, if for some reason the phase of the reproduced signal A advances relative to the clock pulse CP as shown in FIG. Both become "H".
As a result, the output signal F of the latch circuit 6, which is latched by the rising edge of the clock pulse CP, becomes "1" only during one period of the clock pulse CP, as shown in FIG. Figure h
The “0” state continues as shown in . Therefore, the output signal H of the differential circuit 7 which receives the latch outputs F and G as input becomes "1" during one cycle of the clock pulse CP only at the rising edge of the reproduced signal A, as shown in FIG. ” becomes. The output signal H of the differential circuit 6 is taken out through the low-pass filter 8, so that the output signal I becomes as shown in FIG.
This will act on the voltage-controlled variable oscillator 9 as a signal that has increased somewhat. As a result, the clock pulse output from the voltage controlled variable oscillator 9
The oscillation frequency of CP is increased and its phase advances,
As a result, phase matching between the two is automatically performed.

Therefore, in such a configuration, alignment is automatically performed by varying the frequency of the internally oscillated clock pulse in response to phase fluctuations of the reproduced signal as an external input signal. , it is possible to reliably obtain a clock pulse CP that is always synchronized with an external signal. Furthermore, when a slope forming circuit is interposed on the output side of the negative component cut circuit 3 as described above, the output signal D' is
As shown by e in the figure, the positive component differential output has a gentle slope. Therefore, as shown in FIG. 5e, for example, the period _t1 during which the threshold level Vth is exceeded is greatly expanded compared to the case where the differential output remains unchanged. As a result, the tracking range for the phase shift becomes _t1 , and accordingly, the tracking characteristics are significantly improved.

In the above embodiment, a case has been described in which the clock pulse is phase-aligned with respect to the reproduced signal of a digital audio disk, but the present invention is not limited to this.
It can be used to generate clock pulses synchronized with various external signals.

As explained above, the clock pulse generation circuit according to the present invention generates a positive differential output of an external input signal with a slope on the falling side and a signal obtained by applying a DC bias to the differential output from a voltage-controlled variable oscillator. The latch is latched by the generated clock pulse, and the difference between the latch output of the positive polarity differential output to which the slope has been applied and the inverted output of the latch output of the DC biased differential output is determined, and this difference signal is passed through a low-pass filter. By supplying the voltage to the voltage controlled variable oscillator, the oscillation frequency is varied and phase matching is performed. Therefore, even if the phase of the external input signal fluctuates slightly,
A clock pulse can be generated accurately in accordance with the phase of this external input signal. In addition, in the present invention, since a gentle slope is given to the falling part of the positive polarity differential output,
Along with this, there are various excellent effects such as a wider tracking range for phase matching and a significant improvement in tracking characteristics.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the signal format of a digital audio disk, FIG. 2 is a circuit diagram showing an embodiment of a clock pulse generation circuit according to the present invention, FIGS. Figures a-j
2 is an operational waveform diagram of each part of the circuit shown in FIG. 2. FIG. 1... Negative component cut circuit, 2... Differential circuit, 3
... Negative component cut circuit, 4 ... Slope forming circuit, 5 ... Pull-up circuit, 6 ... Latch circuit,
7...Differential circuit, 8...Low pass filter, 9...
...Voltage controlled variable oscillator.

Claims (1)

[Scope of utility model registration request] a differentiating circuit that differentiates an input signal supplied from the outside; a voltage-controlled variable oscillator that generates a clock pulse; and a slope forming circuit that applies a slope to a falling portion of the positive differential output of the differentiating circuit;
a first latch circuit that latches the output of the slope forming circuit in synchronization with the generation of the clock pulse; and a first latch circuit that applies a DC bias to the differentiated output of the differentiation circuit to latch a positive polarity signal in synchronization with the generation of the clock pulse. A second latch circuit sends out the inverted output, a differential circuit calculates the difference in output level between the first and second latch circuits, and the output of the differential circuit is averaged and sent to the voltage controlled variable oscillator. 1. A clock pulse generation circuit comprising: a low-pass filter for supplying a control signal, and obtaining a clock pulse responsive to the input signal from the voltage-controlled variable oscillator.