JPH03175656A - Circuit delay information analyzing system - Google Patents

Abstract

PURPOSE:To facilitate efficient and waste-free analysis in designing a standard cell type LSI even if it contains a CPU core having an abnormally long wiring length by a method wherein a wiring having a practical length is added to the load of a designated call to calculate a delay time. CONSTITUTION:A circuit diagram data input means 1 which inputs a first circuit connection information corresponding to the circuit diagram data of an object circuit, a display means 2 which displays the first circuit connection information and a second circuit connection information which is obtained by renewing the first information, a cell name designating means 3 which designates a cell included in the first and second circuit interconnection information, a wiring length input means 4 which inputs the length of a wiring which is to be a load of the designated cell, a circuit delay calculating means 5 which adds the load of the wiring having the inputted length to the load of the designated cell to calculate the delay time of the cell, a circuit connection information writing means 6 which renews the first and second circuit connection information in accordance with an intermediate result and a final result including the delay time calculated by the means 5, a circuit connection information storing means 7 which stores the first and second circuit connection information, etc., are provided.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit delay information analysis system.

[Conventional technology]

Conventionally, circuit diagram data is input using a circuit diagram input device,
Automatic layout of LSIs is often performed using circuit connection information generated from this circuit diagram data and existing layout cell libraries. In this persimmon design method, it is generally accepted that circuit delay information is analyzed before and after automatic layout. The specific content of this circuit delay information analysis is a combination of design rule checking, delay simulation, delay analysis, etc.

FIG. 5 is a block diagram for explaining the transmission delay time between laid out cells, which is a processing target of a conventional circuit delay information analysis system.

In FIG. 5, the output of cell 51a is output from cell 51b.

It is connected to the input terminal of 51c. Cell 51b.

Input capacitances Cb and Cc exist at the input terminal of 51c, and have sizes represented by CGb and CGc, respectively.

Generally, the propagation delay time is determined by the following equation (1).

Tpd=TpdO+(Cw-1-Cin)XDc...
(1) (TpdO = delay time under swallow load) (Tpd = transmission delay time) (Cw = wiring capacitance 1) (Cin = sum of input capacitance of next stage) (Dc = delay coefficient = transmission delay time per capacitance) Therefore,
The propagation delay time T p da of the cell 51a is as follows (2)
Expressed by the formula.

Tpda=TdpOa+(Cw+ (CGb+CGc
))XDc a---(2)(Dca=cell 5
1a delay coefficient) (T p (l Oa - cell 51 a (7) i delay time under load) In LSI circuit delay information analysis, when considering Cw and Cin for each cell, the circuit operates normally. However, before the CW and Cin of a certain cell are finally determined, various considerations are made regarding the layout area and circuit delay.Actual L S J In design, it is common knowledge that circuit delay information analysis is performed many times in stages.

Below, we will discuss the case of gate array design using the circuit delay information analysis system.

FIG. 6 explains the flow of circuit delay ↑o 'ltt analysis work in actual LSI design.

First, after inputting the circuit diagram data (S61.),
A design rule check (863) is performed and a fan-out check is performed for each cell.

Fan-out is a concept for expressing a limit on the load of each layout cell using f + load capacity value determined by standard f. In reality, the load capacitance value is often expressed by setting the input capacitance value of the inverter to 1.

This is because as the number of fanouts increases, the rise time and fall time of the signal increases, and the accuracy of estimating propagation delay time deteriorates.In addition, when the rise time and fall time become extremely large, This is because data throughput occurs in the flip-flop, making it impossible to maintain normal logic operation. It is necessary to design each cell so that the fan-out number is not exceeded, and the design rule check is used to check for this purpose.

In this check, a check is made regarding the input capacitance of the cell whose value is the load. At the design rule check stage (
1) Cw in formula is not taken into consideration, and only the limitations of Cin are verified.

Subsequently, a delay simulation before automatic layout is performed (S64). At this point, the load due to wiring in the actual layout is unknown, so a delay simulation is performed using a temporary wiring length. This is a simulation in which a load due to a virtual wiring length is uniformly applied to each layout cell. Stage 1 of this delay simulation? In equation (1), Cw is the virtual wiring length, and Cin is the actual f length.

If it is confirmed that there are no problems in this delay simulation, then automatic layout is performed (S66).

As a result of automatic layout, the actual wiring length is determined. Then, a delay simulation is performed using the actual wiring length (S68). In the delay simulation at this stage, the actual wiring length is used as Cw in equation (1), or the actual value is used as Cin.

The automatic layout (S66) l in FIG. 6 is usually performed several times, and the optimum result with respect to chip size and delay operation is selected. That is, delay simulations under load conditions using actual wiring lengths are usually performed simultaneously for multiple circuits.

The above-mentioned design method is based on the premise that in an actual circuit, the load Cw caused by the wiring is sufficiently smaller than the load Cin caused by the input capacitance of the next stage. Based on this premise, we first perform a design rule check to verify that Cw is not present, and eliminate basic errors related to delays.

Next, we perform a delay simulation that takes Cw into consideration.
Since the actual wiring length is unknown until automatic layout is performed, a virtual wiring length is considered. Conventionally, the tentative wiring length used in the field of gate arrays is around 3 strands. The basis for this wiring length is statistical data that when examining the distribution of wiring lengths within a certain chip size range, Daikichi's wiring has a wiring length of 3 mm or less.

Therefore, since the actual wire length after performing the automatic layerer I. is almost the same as the tentative wire length, the probability that an error related to a serious delay will be discovered at this stage is low. Even if the wiring lengths are different, since Cw is sufficiently smaller than Cin, errors that cause large delays are unlikely to occur.

[Problem to be solved by the invention]

The above-mentioned conventional circuit delay information analysis system has a structure that goes through the following stages: analysis that does not take the wiring capacitance Cw into account, analysis that takes into account the wiring capacitance Cw of the temporary wiring length, and analysis that takes into account the wiring capacitance Cw of the actual wiring length. Therefore, it is effective for gate arrays and the like where the premise that Cw((Cin) holds true, but it has the disadvantage that it is not effective for standard cell type LSIs, especially LSIs that include a CPU core.

The reason for this is that LSIs such as microcomputers that include a CPU core always include bus wiring, and the length of the wiring is usually very long. As an actual example, it is not uncommon for the bus wiring length to reach 20 to 30 mm.

In LSIs such as microcomputers, bus wiring and clock signal lines have extremely large wiring capacitance, unlike gate arrays, etc., so delay simulation is performed by matching the average temporary wiring length to these wirings. It's a waste.

As mentioned above, when designing a standard cell type LSI including a CUP core, it is important to check design rules and perform delay simulations that take into account long wiring lengths, and there is no design environment for this. is L
This was a major obstacle in SI development.

An object of the present invention is to provide c p
It is an object of the present invention to provide a circuit delay information analysis system that can perform effective and efficient analysis even for the design of a standard cell LSI including a u-core.

[Means to solve the problem]

The circuit delay information analysis system of the present invention includes a circuit diagram data input means for inputting first circuit connection information corresponding to circuit diagram data of a target circuit; display means for displaying second circuit connection information whose connection information has been updated with intermediate results and final results; cell name designation means for designating cells included in the first and second circuit connection information; A wire length input means for inputting a wire length serving as a load for the cell specified by the cell name designation means, and a delay time of this cell is calculated by adding the load of the input wire length to the specified cell. circuit delay calculation means; circuit connection information writing means for updating the first and second circuit connection information with the intermediate and final results including the delay time calculated by the circuit delay calculation means; and a circuit connection information storage means for storing the second circuit connection information, and an output means for outputting the circuit connection information stored in the circuit connection information storage means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, the circuit diagram data input means 1 inputs first circuit connection information corresponding to the circuit diagram data of the circuit to be parallelized, and the first circuit connection information and this first circuit connection information are intermediate. Display means 2 for displaying the result and second circuit connection information updated based on the final result; cell name designation means 3 for designating the cell name included in the first and second circuit connection information; and the cell name. A wiring length input means 4 for inputting the wiring length to be the load of the cell designated by the designation means 3, and a circuit delay for calculating the delay time of this cell by adding the load of the wiring length input to the designated cell. a calculation means 5; a circuit delay information writing means 6 for updating the first and second circuit connection information with intermediate results and final results including the delay time calculated by the circuit delay calculation means 5; It has a 174 configuration including a circuit connection information storage means 7 for storing the second circuit connection information and an output means 8 for outputting the circuit connection information stored in the circuit connection information storage means 7.

Next, the specific operation of this embodiment will be explained. Specifically, each means of this embodiment has the following configuration, for example.

Circuit diagram data input means 1: Mouse, floppy disk device and circuit diagram editor program display means 2: CRT
Display cell name designation means 3: Keyboard wiring length input means 4: Keyboard circuit delay calculation means 5: Circuit delay 1 (calculation program Circuit delay calculation means 6: Circuit delay information writing program Circuit connection information storage means 7: Magnetic disk connection Position output means 8
: Floppy disk device Also, circuit connection information can be broadly divided into connection-related information, display-related information, input chamber), (2-related information, fan-out limit 4〆f, and display j÷11 information) and l(7, fl? information regarding the 7th layer path name, and f
t r: Year E': Information regarding trench and delay is p>.

+ about connection? 'I report indicates one system of connections between each cell. Information regarding display represents information regarding coordinates, color, size, etc. for displaying each cell. Information regarding the hierarchical path indicates the position in the hierarchical structure where each cell exists using a bus name. The load capacitance has the load side from the output terminal of the cell, and represents the load capacitance due to the wiring and the input capacitance of the next stage. The information regarding the delay represents the delay time when each cell is loaded with =iq, the delay coefficient, and the delay time under the load condition depending on the wiring length.

Consider the circuit diagram data of the circuit diagram shown in FIG. 2 as input data for this system. It is assumed that the circuit connection information corresponding to this circuit diagram data has a structure connected by pointers P shown in FIG. 3. Tags indicated by thick lines in FIG. 3 represent leaf cells (actual data) LC. Table 1 shows the format of the data structure of this property.

As is clear from Table 1, by referring to the property+11 information of each cell, the function name and proper name (unique name) of that cell can be determined. Also, by referring to the input signal name and output signal connection destination, the output signals of other cells to be connected to the cell and the output signals of the cell can be known. The input capacitance of the cell can be found by referring to the input capacitance section. This input capacitance value is used in the circuit delay calculation program of the circuit delay calculation means 5. By referring to fan error 1 to limit, the fan-out limit of the output terminal of the cell can be determined. This fan error limit value will be used in the design rule check described later. Furthermore, by using the circuit diagram editor program display of the circuit diagram data means 1 and the CRT display of the means 2, the origin coordinates and display color of the cell symbol when displaying the cell, and the dimensions at the time of display can be known. In addition, the reference name (hierarchical bus name) of that cell within a specific hierarchical structure can be known. The load capacitance represents the load capacitance due to the wiring from the output terminal of the cell and the input capacitance of the next stage. This load capacitance value is used in the circuit delay calculation program of the circuit delay calculation means 5.

There are broadly three types of information regarding delays. The delay time 0 (when unloaded and loaded), the delay coefficient, and the delay time (when loaded) correspond to T p dO and Dc=Tpd, respectively, described in the section of the prior art.

The operation of performing delay analysis according to this embodiment with respect to the circuit diagram shown in FIG. 2 will be described below.

FIG. 4 is a flow chart for explaining the operation of this embodiment.

The circuit diagram shown in Table 1 and FIG. 2 is input using the mouse of the circuit diagram data input means 1 and the circuit diagram editor program, and is stored in the circuit connection information storage means 7.

The data structure of the circuit connection information at this time is shown in FIG. In the circuit diagram of FIG. 2, it is assumed that the wiring 402 is a bus wiring. Table 2 shows the property information held by the cell 40 in FIG. 3 at this time.

Table 2 Next, a design rule check is performed, but this is done after predicting the load due to the bus wiring. The length of the bus wire to which the wire 402 in FIG. 2 is connected can be roughly determined by designing the initial layout of the chip. Incorporating the load due to the wiring length thus obtained into the circuit connection information already stored in the circuit connection information storage means 7,
This is outputted to the outside of this circuit delay information analysis system by the output means 8, and a design rule check is performed by referring to this circuit connection information.

12'', below, to the flowchart of FIG.

First, the cell 40 is specified using the keyboard, which is the cell name finger/foot means 3 in FIG. This method involves searching the circuit connection information consisting of the list structure shown in Figure 3, and pasting the pointer P of ``10'' on the leaf cells L and C that the pointer P points to. 9 ili.

Next, using the keyboard of the wiring hill input means 11, the wiring length W serving as the load on the ζ cell 40 is input.

Next, from the property information in Table 2, the name 41, 4243.44 of the cell to which the output of cell 40 is connected is referred to.

Next, the input capacity of each cell is referred to from the property information of the cells 41, 42, 43, and 44.

Using the value of the wiring length W and the input capacitance (direction) described above, the following equation described in the circuit delay calculation program of the circuit delay calculation means 5 is calculated.

CW40=WXLC+CG41+CG42+CG43
+CG44 =2. O1pfl (L c - wiring capacitance coefficient [pf/song]) (WxLc=1.2 [p f ]
) (CG41-cell 4■ input capacity a = o2[pr+
>(CG42-cell 42 input ii), = 11.
:! [llf] (CG43 = input capacitance of cell 43 - 0
, 2fpfi) (CG44-input capacitance of cell 44-o,
2(prl,) Next, the value of C wtlo obtained by the circuit delay calculation means 5 is written as i? by the circuit delay information writing means 6. 3 Write into the already written circuit connection information in the branch information storage means 7. The latest property information of the cell 40 stored in the circuit connection information storage means 7 at this time is shown in Table 3.

The property information in Table 3 is read from the circuit connection information storage means 7 and outputted to the outside of the present circuit delay information analysis system by the output means 8.

Refer to the property information of the cell 40 output to the outside,
The value of fan-out limitability, load capacity, and lcw determined previously can be determined. For example, if the capacitance value per fanout is 0.15 pf, fanout limit 10 in Table 3 indicates that the load capacitance must be 1.5 pf or less. In Table 3, the page load capacity is 2 pf, so it is clear that the fan-out limit is violated. This design rule check program is a program that simply compares two numerical values, so it can be configured extremely easily. Since the value of Tpd is not required at the design rule check stage, the fourth
The transmission delay time calculation process (845) in the figure has been omitted.

Table 3 Next, when performing a delay simulation using this embodiment, first specify the cell name 40 and input the wiring length in the same way as in the above design rule check.

Next, using the load capacitance Cw 40 of the cell 40, the cell 40
The cell transmission delay time Tpd40 is determined.

At this time, the transmission delay time and delay coefficient under no load are determined from the property information of the cell 40, and the circuit delay calculation means 5
It is calculated using the following formula written as a program in .

T 1) d 40 = T p d O40+ Cw
40 Xc40 0.8+ 2 X O,12 1,04 [ns] Next, Tpcf-4 obtained by the circuit delay calculation means 5
A value of 0 is written by the circuit delay writing means 6 into the circuit connection information already written in the circuit connection information storage means 7.

Table 4 shows the latest property information of the cell 40 stored in the circuit connection information storage means 7 at this time.

The property information in Table 4 is read from the circuit connection information storage means 7 and outputted to the outside of the water circuit fi extension information analysis system by the output means 8.

A delay simulation is performed with reference to the delay time Tpd40 of the property information of the cell 40 outputted to the outside of Table 4. Tp
d is a value used polaristically in delay simulation.

Delay simulation is performed before and after layout as shown in Figure 6, but in the case of delay simulation before layout, fItC obtained in the initial layout design as described above is used as the wiring length. Just enter it. In delay simulation of layout results, the wiring length extracted from the actual layout results may be input.

In the above description, the cell 40 connected to the bus wiring has been discussed, but a plurality of cells may be specified. Therefore, by repeatedly using this embodiment, it is possible to apply a load according to an arbitrary wiring length to any cell included in the circuit connection information.

Regarding the wiring length, it is possible to use a wiring length close to the actual value obtained in the initial layout design etc. before the wiring. It becomes possible to perform the design rule check and delay simulation as described above using such a load due to the wiring length.

As another embodiment of the present invention, an image scanner or a tablet may be used instead of the mouse of the circuit diagram data input means 1, a liquid crystal display or a plasma display may be used as the display means 2, and the cell name designation means 3 and the wiring length input means 4.
It is also possible to use a mouse as the circuit connection information storage means 7, an optical disk device as the circuit connection information storage means 7, and a magnetic tape device as the output means 8. These hardwares may be those that have been widely used in the past, and no special specifications are required.

Further, it is not necessary to have the circuit connection information processed by the circuit delay calculating means 5 and the circuit delay element n report means 6.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which the delay time is calculated by adding a wire with a wire length that matches the actual situation to the load of a specified cell.
The present invention also has the effect of allowing effective and efficient analysis to be performed on the design of LSIs including CPU cores.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram of a circuit processed by the embodiment shown in FIG. 1, and FIG. 3 is a block diagram of the embodiment shown in FIG. 1. 4 is a flow chart for explaining the operation of the embodiment shown in FIG. 1, and FIG. 5 is a diagram for explaining the operation of the conventional circuit delay information analysis system. FIG. 6 is a flowchart for explaining the operation of the conventional circuit delay information analysis system. 1... Circuit diagram data input means, 2... Display means, 3
. . . Cell name designation means, 4. Wiring length input means, 5.
...Circuit delay calculation means, 6.Circuit delay information a inclusion means, 7.Circuit connection information storage means, 8.Output means,
40-44, 51 a-51 c-cell, 52, 40
2-... Wiring, LC... Leaf cell, P... Pointer, S41-S45 S61-S69... Procedure.

Claims (1)

[Claims] circuit diagram data input means for inputting first circuit connection information corresponding to circuit diagram data of a target circuit;
display means for displaying circuit connection information and second circuit connection information obtained by updating the first circuit connection information with intermediate results and final results; and cells included in the first and second circuit connection information. a cell name specifying means for specifying a cell name, a wiring length input means for inputting a wiring length to be a load of the cell specified by the cell name specifying means, and adding a load of the input wiring length to the specified cell. circuit delay calculation means for calculating the delay time of this cell; and a circuit for updating the first and second circuit connection information with the intermediate and final results including the delay time calculated by the circuit delay calculation means. It has a connection information writing means, a circuit connection information storage means for storing the first and second circuit connection information, and an output means for outputting the circuit connection information stored in the circuit connection information storage means. A circuit delay information analysis system featuring: