JPH031759B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a nonvolatile random access memory device, and more particularly to a nonvolatile random access memory device constructed by combining volatile dynamic memory cells and electrically erasable programmable read only memory (EEPROM). The present invention relates to a nonvolatile random access memory device.

Background of the Technology Recently, in static random access memory devices, nonvolatile memory cells have been created by combining floating gate circuit elements with volatile memory cells, and nonvolatile memory devices using such nonvolatile memory cells have been developed. is being configured. In the static random access memory device described above, the circuit configuration of each memory cell tends to become complicated and the size of each memory cell tends to increase. Since this tendency leads to a decrease in the reliability and degree of integration of memory devices, it is desired to improve the reliability and the degree of integration of the memory device by improving the circuit configuration.

Prior Art and Problems FIG. 1 shows a circuit diagram of a memory cell used in a conventional non-volatile static random access memory device. This memory cell is MIS
(Metal-insulator-semiconductor) transistors T ₁ , T ₂ ,
It is composed of a volatile static memory cell section 1 including transistors _T3 and _T4 , and a nonvolatile memory cell section 2 including an MIS transistor _T6 having a floating gate. This memory cell can store 1 bit of data. In addition to the MIS transistor T ₆ , the nonvolatile memory cell section 2 includes an MIS transistor T ₅ , a tunnel capacitor TC ₁ and
TC ₂ , a capacitor module CM, and capacitors C ₁ and C ₂ . Note that a capacitor that produces a tunnel effect when a voltage is applied between its electrodes is called a tunnel capacitor.

In the circuit of FIG. 1, the static memory cell section 1 has a flip-flop type configuration similar to that used in conventional volatile static random access memory devices. Data is written and read in the static memory cell section 1 via transfer gate transistors TG connected to nodes _N1 and _N2 . In the nonvolatile memory cell section 2, a circuit including the gate of the MIS transistor _T6 is in a floating state separated from other circuits. Data can be stored depending on whether or not electrons are injected into this floating gate circuit.
Therefore, data in the static memory cell section 1 is transferred to the nonvolatile memory cell section 2 before the power supply Vcc of the memory device is cut off, and data is transferred from the static memory cell section 2 conversely when the power supply Vcc is turned on. Transfer data to memory cell section 1. That is, by using a recall configuration, it is possible to realize a high-speed nonvolatile memory device.

For example, it is assumed that predetermined data is written in the static memory cell section 1, the node _N1 is at a low level (Vss), and the node _N2 is at a high level (Vcc). If data in the static memory cell section 1 is to be transferred to the nonvolatile memory cell section 2 in this state, the control power supply _VHH is raised from the normal 0V state to, for example, 20 to 30V. At this time, since the node _N1 is at a low level, the transistor _T5 is in a cut-off state, and since the electrode _D1 of the capacitor module CM is in a floating state, the capacitance is reduced by raising the power supply _VHH . The coupling pulls the gate of transistor _T6 to a high voltage. Since the capacitance between the electrodes D ₁ and D ₂ and the capacitance between the electrodes D ₁ and D ₃ of the capacitor module CM are both sufficiently larger than the capacitance of the tunnel capacitors TC ₁ and TC ₂ , the transistor T The gate voltage of ₆ is raised to a voltage approximately close to the power supply V _HH . As a result, a high voltage is applied across the tunnel capacitor _TC1 , and electrons are injected from the power supply Vss (ground potential) to the gate of the transistor _T6 , that is, the floating gate side due to the tunneling phenomenon, and the floating gate is charged with a negative charge and the transistor _T6 is turned off. This negative charge is retained for a long period of time even after the power supplies Vcc and _VHH of the memory device are cut off, and data is stored non-volatilely.

When the node _N1 of the static memory cell section 1 is at a high level and the node _N2 is at a low level, electrons are extracted from the floating gate side of the transistor _T6 to the power supply _VHH side, and a positive charge is placed on the floating gate. is charged. For details, please refer to the special application published in 1983.
It is described in the specification of No. 191039.

Next, when the power is turned on, the nonvolatile memory cell section 2
The operation when transferring data to the volatile memory cell unit 1 will be explained. First, from a state where both power supplies Vcc and V _HH are 0V (=Vss), change only the power supply Vcc, for example.
Increase to 5V. At this time, if the transistor T ₆
If electrons are accumulated in the floating gate of the transistor _T6 , the transistor T6 is in a cut-off state, and the connection between the capacitor _C2 and the node _N2 is cut off. Since the node _N1 is connected to the capacitor _C1 , when the power supply Vcc is raised, the flip-flop circuit is set to a low level on the node _N1 side, which has a large load capacity, and a high level on the node _N2 side. Conversely, if the floating gate of transistor _T6 is charged with positive charges, transistor _T6 is turned on, and node _N2 and capacitor _C2 are connected. Since the capacitance of capacitor _C2 is larger than that of capacitor _C1 , the flip-flop circuit of volatile memory cell section 1 is set so that node _N2 becomes low level and node _N1 becomes high level when the power supply Vcc is raised. be done. In this way, data corresponding to the charge on the floating gate of the transistor _T6 is set in the volatile memory cell section 1, and a nonvolatile memory device is constructed by using the circuit shown in FIG.

However, in the conventional device described above, a static flip-flop circuit is used as the volatile memory cell section, and the number of circuit elements increases, making it not necessarily suitable for high integration of the device. Another problem is that it requires a plurality of tunnel capacitors, and it is difficult to control the thickness and quality of the insulating film in the manufacture of integrated circuits, making it difficult to improve yields.

OBJECT OF THE INVENTION In view of the problems in the conventional device described above, an object of the present invention is to provide a system based on the concept of combining a volatile dynamic random access memory cell with a non-volatile memory cell section using one EEPRON. The object of the present invention is to reduce the number of circuit elements in a memory device to enable high integration and to improve manufacturing yield.

Structure of the Invention In the present invention, one memory cell is configured by pairing a volatile memory cell section and a nonvolatile memory cell section for saving storage information in the volatile memory cell section, and The functional memory cell section has a capacitor section that stores an amount of charge according to the information to be stored, a transfer gate transistor connected between the capacitor section and the bit line, a control gate and a floating gate, and stores electrons. a double-gate nonvolatile memory cell transistor in which injection is performed by tunnel effect; a recall transistor for transferring information stored in the nonvolatile memory cell transistor to the capacitor section in response to a recall signal; a first transistor whose gate is connected to the capacitor section and turns on and off according to information stored in the capacitor section; and a second transistor connected between the first transistor and the control gate.
a diode element connected to the control gate, a first write voltage is applied to the control gate via the diode element, and a second write voltage is then applied to the drain of the nonvolatile memory cell transistor. Non-volatile random access characterized in that information in the volatile memory cell section is written into the non-volatile memory cell section by applying a write voltage of and making the second transistor conductive. A memory device is provided.

Embodiment of the Invention A memory cell used in a non-volatile random access memory device as an embodiment of the present invention is a second embodiment of the present invention.
As shown in the figure. This memory cell comprises a volatile dynamic memory cell section 3 and a non-volatile memory cell section 4. The volatile dynamic memory cell section 3 is composed of the MIS transistor _T11 and the gate capacitance of the MIS transistor Tc as a capacitor section. A single capacitor may be used as shown by the dashed line. The transfer gate transistor _T11 connects the bit line BL and the first transistor Tc.
The gate of transistor _T11 is connected to the word line WL. The source of the transistor Tc is the power supply, which is the common terminal side of the power supply.
Connected to Vss (usually 0V). The transistor Tc shares the function of the capacitor part of the volatile dynamic memory cell part 3 and the function of the first transistor of the nonvolatile memory cell part 4. A node N ₁₁ is a connection point between the transistor T ₁₁ and the gate of the transistor Tc.

In addition to the transistor Tc, the nonvolatile memory cell section 4 includes a recall transistor T _A , a transistor T _E functioning as a diode element, a second transistor T _P , and an EEPROM as a nonvolatile memory cell transistor with a double gate structure.
( _TM ). All transistors are MIS
A transistor is used. A second write power supply V _H /AR whose voltage can be switched in two steps is connected to the drain of the EEPROM, the source of the EEPROM is connected to the drain of the transistor _TA , and the source of the transistor _TA is connected to the node _N11 . Ru. An array recall signal AR is supplied to the gate of the transistor T _A.

The first write power supply V _H1 is connected to the drain and gate of the transistor T _E , and
The source of T _E is the EEPROM control gate
Connected to CG and the drain of transistor T _P , respectively. The program signal PGM is supplied to the gate of the transistor T _P , and the source is connected to the drain of the transistor T _P.

The operation of the aforementioned memory cell will be explained. When transferring data from the volatile dynamic memory cell section 3 to the nonvolatile memory cell section 4, first the signal
PGM, AR, and power supply V _H /AR are set to 0V, and power supply V _H1 is increased from 0V to approximately 20V.
Since the transistor T _E is in the on state and the transistor T _P is in the off state, the control gate CG of the EEPROM rises to about 20V. EEPROM
has a structure as shown in FIG. 3, and is represented by the equivalent circuit shown in FIG. Therefore, when a voltage of about 20V is applied between the control gate CG and the drain D, the capacitance between the control gate CG and the floating gate FG becomes a tunnel capacitor.
Since the capacitance between the floating gate FG and the drain D acting as TCα is sufficiently larger, most of the voltage is applied between the floating gate FG and the drain D due to capacitive coupling. In this state, the EEPROM becomes an erase state, and the floating gate FG
Electrons are injected into it and it becomes negatively charged. Then, when the power supply V _H1 is lowered to 0V, the transistor T _E
turns off, the charge on the control gate CG of the EEPROM does not flow away, and the voltage of the control gate CG maintains approximately 20V. If the signal PGM is set to a high level and the gate voltage of the transistor Tc is at a high level, the charge of the control gate CG flows to the power supply Vss, and the voltage becomes 0V.
decreases to If the gate voltage of the transistor Tc is at a low level, the transistor Tc is off, so the charge on the control gate CG does not change and the voltage does not drop. In this state, the power supply V _H /AR
When increasing from 0V to about 20V, the transistor
When the gate of Tc is low level, the voltage of the drain D of EEPROM is about 20V, and the voltage of the control gate CG
The voltage remains unchanged at approximately 20V, and the EEPROM remains erased. When the gate of transistor Tc is at a high level, the voltage at the drain of the EEPROM is approximately 20V, the voltage at the control gate CG is 0V, the floating gate FG is charged with positive charge, and the EEPROM is written. As mentioned above, depending on whether the node _N11 of the volatile dynamic memory cell section 3 is at a high level or a low level,
The floating gate FG of the EEPROM is charged with a positive charge or charged with a negative charge to retain the contents of the dynamic memory cell.

When the contents stored in the nonvolatile memory cell section 4 are transferred to the volatile dynamic memory cell section 3, that is, in the case of array recall, the following operation is performed. i.e. power supply V _H1 and signal
PGM is set to low level (0V), signal AR is set to high level (5V), power supply V _H /AR is set to Vcc voltage (5V), and word line is set to low level. If the EEPROM floating gate FG is charged with positive charge,
A voltage of 5V from the power supply V _H /AR is supplied to node N ₁₁ through the drain and source of the EEPROM and transistor _TA , charging the memory capacitor to a high level. When the floating gate FG of EEPROM is charged with negative charge,
There is no conduction between the drain D and source S of the EEPROM, and the memory capacitor constituted by the transistor Tc of the volatile dynamic memory cell section 3 is not charged from the power supply V _H /AR. In this way, the data transferred and stored in the nonvolatile memory cell section 4 can be reproduced in the volatile dynamic cell section 3.

used in the nonvolatile memory cell section 4
I will provide a supplementary explanation about EEPROM. As shown in FIG. 3, in the EEPROM, two n ⁺ regions are formed on a silicon substrate (Sisub) and are used as a drain D and a source S. Furthermore, in addition to the control gate CG as a gate, a floating gate FG is provided between the control gate CG and the silicon substrate, and a part of the drain of the floating gate FG is insulated with a thin silicon oxide (SiO ₂ ) insulating film. and is configured to cause electron tunneling between them. Therefore, the equivalent circuit of the EEPROM is as shown in FIG.

In the circuit of this embodiment, the gate capacitance of the transistor Tc is used as the capacitor section of the volatile dynamic memory cell section 3, and no particular capacitor is added. However, as shown by the broken line in FIG. It is also possible to reduce the size of Tc by providing a capacitor. Further, although the transistor T _E is used as the diode element, other circuits may be used as long as they function as a diode.

Effects of the Invention According to the present invention, it is possible to reduce the number of circuit elements in a nonvolatile memory device to achieve high integration, and to reduce the use of a floating gate circuit element such as a tunnel capacitor to one, thereby improving manufacturing yield. It is possible to realize an improvement in

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory cell used in a conventional nonvolatile static random access memory device, and FIG. 2 is a circuit diagram of a memory cell used in a nonvolatile random access memory device as an embodiment of the present invention. , FIG. 3 is a sectional view showing the structure of the EEPROM used in the memory cell of FIG. 2, and FIG. 4 is an equivalent circuit diagram of the EEPROM of FIG. 3. 1...Volatile static memory cell section, 2...Nonvolatile memory cell section, 3...Volatile dynamic memory cell section, 4...Nonvolatile memory cell section, BL...
Bit line, C ₁ , C ₂ ...capacitor, CG...control gate, CM...capacitor module, D...
Drain, D ₁ , D ₂ , D ₃ ... Electrode, FG... Floating gate, S... Source, T ₁ , T ₂ , T ₃ , T ₄ ,
T ₅ , T ₆ , T ₁₁ , T _A , T _C , T _E , T _P ...MIS transistor, TCα...tunnel capacitor, T _M ...
EEPROM, WL...word line.

Claims (1)

[Scope of Claims] 1. One memory cell is configured by pairing a volatile memory cell section and a nonvolatile memory cell section for saving storage information in the volatile memory cell section, and The memory cell section has a capacitor section that stores an amount of charge according to information to be stored, a transfer gate transistor connected between the capacitor section and the bit line, a control gate and a floating gate, and has a control gate and a floating gate. a non-volatile memory cell transistor with a double gate structure in which this is achieved by a tunnel effect; a recall transistor for transferring information stored in the non-volatile memory cell transistor to the capacitor section in response to a recall signal; , a first transistor whose gate is connected to the capacitor section and which is turned on and off according to information stored in the capacitor section; and a second transistor connected between the first transistor and the control gate. a diode element connected to the control gate, applying a first write voltage to the control gate via the diode element, and then applying a second write voltage to the drain of the nonvolatile memory cell transistor; A nonvolatile random access memory device characterized in that information in the volatile memory cell section is written into the nonvolatile memory cell section by applying a voltage and making the second transistor conductive. . 2. The non-volatile random access memory device according to claim 1, wherein the capacitor section is constituted by the gate capacitance of the first transistor.