JPH03178155A - Ic package - Google Patents

Ic package

Info

Publication number
JPH03178155A
JPH03178155A JP2336963A JP33696390A JPH03178155A JP H03178155 A JPH03178155 A JP H03178155A JP 2336963 A JP2336963 A JP 2336963A JP 33696390 A JP33696390 A JP 33696390A JP H03178155 A JPH03178155 A JP H03178155A
Authority
JP
Japan
Prior art keywords
leads
package
bent
type
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2336963A
Other languages
Japanese (ja)
Inventor
Kichisho Ro
盧 吉燮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH03178155A publication Critical patent/JPH03178155A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/421Shapes or dispositions
    • H10W70/424Cross-sectional shapes
    • H10W70/427Bent parts
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To prevent short-circuiting between leads generated, due to an interval between fine leads while maintaining a same interval between leads for each system by placing an IC package on a circuit substrate, where a connection point is formed at a position that corresponds to the bent part of a number of gull wing type and J-type leads. CONSTITUTION: A large number of leads 10N of an IC package 10 have gull wing type bent leads G1-G6 each of which has a bent part G1A and the like that is bent in gull wing type. Leads J1-J5 that are bent in J-type are provided between the gull wing type leads G1-G6, each lead is bent in J-type, and a bent part J1A, where an edge part J1B is brought close to the bottom surface 10A of the IC package 10 is provided. Each lead of the IC package 10 in this form is connected to each corresponding point from among a number of connection point formed in a circuit substrate 6, thus relatively increasing the gap between leads when connected to the substrate 6 and preventing electrical short- circuiting.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はICパッケージ(IntegratedCir
cuit Package )に関するもので、特にリ
ードを交互にガル型(Gulf Type )及びJ型
(J Type)に折曲した組合せ型ICパッケージに
関するものである。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention is applied to IC packages (Integrated Circuits).
The invention relates to a combination type IC package in which leads are bent alternately into a Gull type and a J type.

〔従来の技術〕[Conventional technology]

一般的に、すべての製造工程が完了後、ICパッケージ
は両側面の多数のリードを折曲する成形工程(Form
ing Process )において\リードをガル型
まはたJ型にフォーミングする。
Generally, after all the manufacturing processes are completed, the IC package is manufactured through a forming process (Form) that involves bending a large number of leads on both sides.
ing Process), form the lead into a gull or J shape.

即ち、第1A図は多数のリードINを有するICパッケ
ージ1の各リードIAを段階形態のガル型に折曲した折
曲部IBを示したものであり、第1B図は多数のリード
2Bを有するICパッケージ2の各リード2AをJ型に
折曲された端部2Dを上記ICパッケージ2の底面2C
に近接された折曲部2Bを夫々図示する。
That is, FIG. 1A shows a bent part IB in which each lead IA of an IC package 1 having a large number of leads IN is bent into a stepped gull shape, and FIG. 1B shows a bending part IB having a large number of leads 2B. The J-shaped bent ends 2D of each lead 2A of the IC package 2 are connected to the bottom surface 2C of the IC package 2.
The bent portions 2B are shown close to each other.

一般的に、各々のICパッケージ1および2の両側のリ
ードIA及び2人は第1A図並びに18図に図示されて
いる通り、ガル型またはJ型等に折曲し、用途によって
選択的に使用している。従って、このような各々のIC
パッケージ1及び2の各々のリード1A及び2Aの折曲
部1B及び2Bは回路が構成される基板の予定位置に表
面実装技術(Surrace Mount Techn
ology)により接続される。
Generally, the leads IA and 2 on both sides of each IC package 1 and 2 are bent into a gull shape or a J shape, as shown in FIGS. 1A and 18, and are used selectively depending on the application. are doing. Therefore, each such IC
The bent portions 1B and 2B of the leads 1A and 2A of the packages 1 and 2 are mounted using surface mount technology (Surface Mount Technique) at the predetermined positions on the board on which the circuit is formed.
connected by

しかし、このようにtCパッケージの多数のリードを回
路基板に接続する表面実装技術によると、各リード間の
間隔が非常に狭い関係上にあるためリード間に生じる電
気的短絡を防止することができなかった。即ち、一般的
にガル型またはJ型に折曲された各々のリード(LA又
は2A)において、第1C図に見る通り、互いに隣接す
るり−ドL1及びL2間のピッチ9は約1.27mmで
あり、各リード1又は2Aの幅Wは約0.635m+*
である。
However, according to surface mount technology that connects a large number of leads of a TC package to a circuit board in this way, the distance between each lead is very narrow, making it impossible to prevent electrical short circuits occurring between the leads. There wasn't. That is, in each lead (LA or 2A) that is generally bent in a gull shape or a J shape, the pitch 9 between the adjacent leads L1 and L2 is about 1.27 mm, as shown in FIG. 1C. The width W of each lead 1 or 2A is approximately 0.635m+*
It is.

従って、実質的な両リードL1及びL2間の間隔Iはほ
ぼ0.635+++mになる。結果的にICパッケージ
の各リードを基板上に接続した場合、各リード間に間隔
が微細であるため、リード間の短絡が発生する。
Therefore, the actual distance I between both leads L1 and L2 is approximately 0.635+++m. As a result, when the leads of the IC package are connected to the substrate, short circuits occur between the leads because the intervals between the leads are minute.

第1D図は前述の通り、ICパッケージの各リードに対
応して接続される回路基板上の接続点を図示したもので
ある。
As described above, FIG. 1D illustrates the connection points on the circuit board that are connected to each lead of the IC package.

例えば、第1A図のようにガル型に折曲されたICパッ
ケージ1が点線で示されるように、回路基板5上に接着
されるものと仮定すると、上記ICパッケージ1の多数
のリードINの各リード1Aの折曲部IBは、基板5の
多数の接続点5N中上記各リードLAに対応する各々の
接続点(Xl。
For example, if it is assumed that the IC package 1 bent into a gull shape as shown in FIG. The bent portion IB of the lead 1A is located at each connection point (Xl) corresponding to each lead LA among the many connection points 5N of the board 5.

・・・・・・・・・XN)に順次的に一直線に接続され
る。従って、第1C図に図示した通り実質的各リード間
の間隔Iが微細であるため(1−0,635關)、各リ
ード間の電気的短絡が発生し、それによって、回路の電
気不良発生率が高くなる。同様に、第1B図に図示の如
く、J型のリードを有するICパッケージも上述の問題
点が発生する。そこで、このような問題点を解決するた
め、接続工程時に細密なリード間の間隔を維持すること
ができる高価な表面実装装置が必要となり経済的負担を
大きくなっていた。
. . . XN) are sequentially connected in a straight line. Therefore, as shown in FIG. 1C, since the distance I between the leads is substantially small (1-0,635 degrees), an electrical short circuit occurs between the leads, thereby causing an electrical failure in the circuit. rate becomes higher. Similarly, an IC package having a J-shaped lead as shown in FIG. 1B also suffers from the above-mentioned problem. Therefore, in order to solve these problems, an expensive surface mounting device that can maintain a fine spacing between the leads during the connection process is required, which increases the economic burden.

〔課題を解決するための手段〕[Means to solve the problem]

従って、発明の目的は上述の問題点を解決するため、既
存の各体系別リード間を同一の間隔を維持しつつ、微細
なリード間の間隔により発生し得る各リード間の短絡を
防止することができるガル型及びJ型の組合せ型ICパ
ッケージを提供することにある。
Therefore, in order to solve the above-mentioned problems, it is an object of the present invention to maintain the same spacing between the leads of each existing system and to prevent short circuits between the leads that may occur due to the fine spacing between the leads. The purpose of the present invention is to provide a combination type IC package of a gal type and a J type.

本発明による組合せ型ICパッケージによれば、各々ガ
ル型に折曲された折曲部を有する多数のガル型のリード
と、上記多数のガル型のリードの間に交互的に配列され
て、しかも各々J型に折曲された端部が設けられた折曲
部を有する多数のJ型リードを形威し、上記多数のガル
型並びにJ型リードの折曲部に対応する位置に接続点が
形成された回路基板に装着できるように構成したことを
特徴とする。
According to the combination type IC package according to the present invention, a large number of gull-shaped leads each having a bent portion bent in a gull shape, and a plurality of gull-shaped leads arranged alternately between the plurality of gull-shaped leads, and A large number of J-shaped leads each having a bent portion with a J-shaped end are formed, and connection points are provided at positions corresponding to the bent portions of the large number of gull-shaped and J-shaped leads. It is characterized by being configured so that it can be attached to a formed circuit board.

〔実施例〕〔Example〕

以下、本発明を添付された図面を参照して詳細に説明す
る。
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

第2A図は、本発明によるICパッケージの斜視図を、
第2B図は第2A図の正面図を各々表わしている。
FIG. 2A shows a perspective view of an IC package according to the present invention.
FIG. 2B each represents a front view of FIG. 2A.

本発明の最も大きな特徴は、ICパ・7ケ一ジ両側面の
多数個のリードをガルまたはJ型に交互組合せたICパ
ッケージを提供するところにある。
The most significant feature of the present invention is that it provides an IC package in which a large number of leads on both sides of an IC package are alternately combined in a gal or J shape.

第2A及び2B図を参照すれば、本発明のICパッケー
ジ10の多数のリードIONは各々ガル型折曲された第
1リードG1、第3リードG2、第5リードG3及び第
7リードG4、第9リードG5、第11リードG6を備
えているが、各々ガル型に折曲された折曲部CIAを具
備し、上記、各々のガル型リード等Gl、G2.G3.
G4゜G5及びG6の間には、各々J型に折曲された第
2リードJ1、第4リードJ2、第6リードJ3及び第
8リードJ4、第10リードJ5を備え、各々J型に折
曲させ、端部JIBを上記ICバ・ノケージ10の底面
10Aに近接させた折曲部JIAを具備する。
Referring to FIGS. 2A and 2B, the multiple leads ION of the IC package 10 of the present invention are a first lead G1, a third lead G2, a fifth lead G3, a seventh lead G4, and a third lead G4, which are bent into a gull shape. The 9th lead G5 and the 11th lead G6 are each provided with a bent portion CIA bent into a gull shape, and each of the gull type leads Gl, G2 . G3.
G4゜Between G5 and G6, there are provided a second lead J1, a fourth lead J2, a sixth lead J3, an eighth lead J4, and a tenth lead J5, each of which is bent into a J shape. A bent portion JIA is provided which is bent and has an end portion JIB close to the bottom surface 10A of the IC bar cage 10.

このような形態のICパッケージ30の各々のリードは
第2C図に図示されているような回路基板6内に形成さ
れた多数の接続点6N中、夫々対応する接続点に接続さ
れる。即ち、ICパッケージ10が点線にて図示されて
いるように回路基板6上に装着されるものと仮定すれば
、上記夫々のガル型に折曲された折曲部CIAを有する
第1゜第3、第5、第7、第9及び第11リードGl。
Each lead of the IC package 30 having such a configuration is connected to a corresponding connection point among a large number of connection points 6N formed in the circuit board 6 as shown in FIG. 2C. That is, assuming that the IC package 10 is mounted on the circuit board 6 as shown by the dotted line, the first, third and third parts having the respective gull-shaped bent portions CIA are provided. , fifth, seventh, ninth and eleventh leads Gl.

G2.G3.G4.G5及びG6の各々は回路基板6内
の“X“列に位置する夫々の接続点X1゜X2.X3.
X4.X5及びX6に相互対応して接続され、上記夫々
J型に折曲させた折曲部JIAをh″する第2、第4、
第6、第8及び第10リードJl、J2.J3.J4及
びJ5は回路基板6内の“Z゛列に位置する各々の接続
点Zl。
G2. G3. G4. G5 and G6 each connect to a respective connection point X1°X2. located in the "X" column in the circuit board 6. X3.
X4. A second, a fourth,
6th, 8th and 10th leads Jl, J2. J3. J4 and J5 are respective connection points Zl located in the "Z" column in the circuit board 6.

Z2.Z3.Z4及びz5に相互対応して接続される。Z2. Z3. Connected to Z4 and Z5 in a mutually corresponding manner.

この時、回路基板6内の“X”列及び“Z”は各々予定
されている距離を保つようになる。従って、上記ICパ
ッケージのガル型並びにJ型をもって組合せられた多数
のリード6N等は第1D図に図示された多数の接続点の
間隔よりもっと広い間隔を持って接続される。即ち、第
1D図の互いに隣接するリード(Ll及びL2の間隔1
は約0.635關であるのに対して、第2C図のリード
等、例えば、リードG1及びJlの間隔1は約2 am
になるので、はぼ3倍程度の広い距離を維持することが
できる。
At this time, the "X" column and "Z" in the circuit board 6 maintain a predetermined distance from each other. Therefore, a large number of leads 6N, etc., which are combined in the gull type and J type of the IC package, are connected with a wider interval than the interval between the multiple connection points shown in FIG. 1D. That is, the distance between the adjacent leads (Ll and L2 of FIG.
is about 0.635 mm, whereas the spacing 1 of leads G1 and Jl, such as the leads in FIG. 2C, is about 2 am.
Therefore, it is possible to maintain a distance approximately three times as wide.

尚、図面上ではICパッケージの多数のリードがICパ
ッケージ本体両側に形成されているものを示すが、明細
書の複雑性を避けるため一方だけを例に取って説明して
いる。
Although the drawings show an IC package in which a large number of leads are formed on both sides of the IC package body, only one lead will be explained as an example to avoid complicating the specification.

又1個のICパッケージの夫々のリードをガル型及びJ
型に交互組合せて折曲させる方法は折曲金型(Form
ing Press )のパンチ及びダイ(Die )
で本発明の要求に適合するように加工することができる
ので、大きな問題とはならない。
Also, each lead of one IC package is connected to gal type and J type.
Form
ing Press) punches and dies (Die)
Since it can be processed to meet the requirements of the present invention, this does not pose a major problem.

〔発明の効果〕〔Effect of the invention〕

従って、ガル型とJ型を交互に組合せた形態のリードを
有する本発明のICパッケージはガル型またはJ型中ど
ちらかひとつの単一形態でリードを折曲した従来のIC
パッケージより、基板に接続した場合夫々のリード間の
間隔が相対的に広くすることができ電気的短絡を防止す
ることができ、その粘果的に製品の不良率を減少させる
効果を有する。
Therefore, the IC package of the present invention having leads in the form of an alternating combination of the gull type and the J type is different from the conventional IC package in which the leads are bent in a single form of either the gull type or the J type.
Compared to a package, when connected to a substrate, the distance between each lead can be made relatively wider, thereby preventing electrical short circuits, which in turn has the effect of reducing the defective rate of products.

【図面の簡単な説明】[Brief explanation of drawings]

第1A図は従来技術によってリードをガル型に折曲させ
た状態のICパッケージ正面図、第1B図は従来技術に
よってリードをJ型に折曲させた状態のICパッケージ
正面図、第1C図はICパッケージの互いに隣接するリ
ード間のピッチ並びに幅を示すリードの部分正面図、第
1D図は第1A図又は第1B図の各リードと対応する接
続点をひとつの例として示した牙湾の平面図、第2A図
は本発明の組合せ型ICパッケージの斜視図、第2B図
は本発明の第2A図の組合せ型ICパッケージ正面図、
第2C図は本発明の組合せ型ICパッケージとリードと
対応する回路基板内の接続点を示す平面図である。
FIG. 1A is a front view of an IC package with the leads bent into a gull shape using the prior art, FIG. 1B is a front view of the IC package with the leads bent into a J shape using the prior art, and FIG. 1C is a front view of the IC package with the leads bent into a J shape using the prior art. FIG. 1D is a partial front view of the leads showing the pitch and width between adjacent leads of the IC package, and FIG. 1D is a plan view of Fang Bay showing each lead and the corresponding connection point in FIG. 1A or FIG. 1B as an example. FIG. 2A is a perspective view of the combination type IC package of the present invention, and FIG. 2B is a front view of the combination type IC package of FIG. 2A of the present invention.
FIG. 2C is a plan view showing the combination type IC package of the present invention, the leads, and the corresponding connection points in the circuit board.

Claims (1)

【特許請求の範囲】 多数の接続点が形成された回路基板に装着される多数の
リードを、底面に有するICパッケージにおいて、 夫々ガル型に折曲された折曲部を有する多数のガル型の
リードと、 前記多数のガル型のリード間に交互に配列され、かつ、
前記ICパッケージの底部に近接されるように夫々J型
に折曲された端部を有する折曲部が備えられた多数のJ
型リードとを有し、前記多数のガル型及びJ型リードの
折曲部に対応する位置に接続点が形成された回路基板に
装着できるように構成したことを特徴とするガル型及び
J型の組合せICパッケージ。
[Claims] In an IC package that has a large number of leads attached to a circuit board on which a large number of connection points are formed on the bottom surface, a large number of gull-shaped leads each having a bent part bent into a gull shape are provided. leads and the plurality of gull-shaped leads are arranged alternately, and
A plurality of J bending parts each having a J-shaped bent end so as to be close to the bottom of the IC package.
gull type and J type leads, and configured to be able to be mounted on a circuit board having connection points formed at positions corresponding to the bent portions of the large number of gull type and J type leads. combination IC package.
JP2336963A 1989-11-30 1990-11-30 Ic package Pending JPH03178155A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019890017549A KR910010682A (en) 1989-11-30 1989-11-30 Mixed I.C package of Gull Type and J Type.
KR89-17549 1989-11-30

Publications (1)

Publication Number Publication Date
JPH03178155A true JPH03178155A (en) 1991-08-02

Family

ID=19292315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2336963A Pending JPH03178155A (en) 1989-11-30 1990-11-30 Ic package

Country Status (2)

Country Link
JP (1) JPH03178155A (en)
KR (1) KR910010682A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993019488A1 (en) * 1992-03-23 1993-09-30 National Semiconductor Corporation Surface mountable integrated circuit package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62276864A (en) * 1986-05-26 1987-12-01 Hitachi Ltd Semiconductor device
JPS6482659A (en) * 1987-09-25 1989-03-28 Mitsubishi Electric Corp Semiconductor device
JPH0236051B2 (en) * 1984-05-22 1990-08-15 Kogyo Gijutsuin

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0236051B2 (en) * 1984-05-22 1990-08-15 Kogyo Gijutsuin
JPS62276864A (en) * 1986-05-26 1987-12-01 Hitachi Ltd Semiconductor device
JPS6482659A (en) * 1987-09-25 1989-03-28 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993019488A1 (en) * 1992-03-23 1993-09-30 National Semiconductor Corporation Surface mountable integrated circuit package

Also Published As

Publication number Publication date
KR910010682A (en) 1991-06-29

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