JPH03178170A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the drain breakdown strength of an offset gate MOSFET of SOI(silicon on insulator) structure, and at the same time increase ON-current, by electrically connecting a drain lower part electrode with a gate electrode via an inverter. CONSTITUTION:Under a drain diffusion layer 7 and an adjacent semiconductor layer 3, a drain lower part electrode 9 is formed via an insulating film 10 in an adjacent manner. In the OFF-state of an MOSFET, the same potential VCC as a potential to be applied to the drain diffusion region 7, e.g. a high potential VCC, is applied to the drain lower electrode 9, via an inverter. In the ON-state of the FET, a potential to be applied to the drain diffusion region 7, e.g. a low potential VSS opposite to the potential VCC, is applied to the drain lower part electrode 9, via the inverter. Thereby the drain breakdown strength of an offset gate type MOSFET of SOI structure can be improved, and at the same time, the ON-current can be increased, so that the driving capability and the operating speed of a semiconductor IC using MOSFET's can be increased.

Description

[Detailed description of the invention]

[Summary] Regarding the improvement of the element structure of semiconductor devices, especially power MO8FETs with an SOI structure, we have developed a power MO8FET with a Sol structure and an offset gate type.
In order to improve the drain breakdown voltage of the FET and increase the on-current at the same time, a semiconductor substrate, a base insulating film provided on the semiconductor substrate, and a semiconductor layer provided on the base insulating film are used. , a source diffusion region and a drain diffusion region formed apart from each other in the semiconductor layer, and a space between the source diffusion region and the drain diffusion region, in contact with the drain diffusion region and spaced apart from the source diffusion region. a gate insulating film formed on the semiconductor layer; a gate electrode provided on the gate insulating film on a space between the source diffusion region and the offset region; A lower drain electrode is selectively provided directly below the diffusion region and the offset region adjacent to each other through an insulating film, and the lower drain electrode is electrically connected to the gate electrode via an inverter. configured. [Industrial Application Field] The present invention relates to semiconductor devices, particularly power MO8F with Sot structure.
This article relates to improvements in the element structure of ET. Demand for ICs incorporating power MO8FETs is increasing in applications that require high voltage and advanced control, such as display panel drives and direct motor drives, and they have higher drain withstand voltage and lower on-resistance. low power MO8
FET is required. [Conventional technology] Among the conventionally developed power MO8FETs, SOI
The conventional structure of the (Silicon On In5ulator) structure is schematically shown in the side cross-sectional view of FIG. ), 4 is a gate insulating film, 5 is a gate electrode, 6 is a source diffusion region (e.g. n" type), 7 is a drain diffusion region (e.g. n+ type), and 8 is an offset low concentration region (e.g. n-type). , A. tr indicates an offset portion. In the above Sol structure, the semiconductor layer 3 in the element formation region
is formed on the base insulating film 2, the individual elements can be completely electrically isolated by performing element isolation in the lateral direction. Therefore, by thinning the semiconductor layer 3 in the element formation region, the offset portion Aatt in the figure can be easily completely depleted in the vertical (thickness) direction. Since the vertical electric field does not increase even if the voltage is further increased, junction breakdown between the drain diffusion region 7 and the substrate 1 does not occur as in a MOSFET formed directly on a bulk semiconductor. Therefore, a MOSFET is formed that has a higher drain breakdown voltage than a bulk semiconductor, that is, a MOSFET that is formed directly on a semiconductor substrate. [Problem to be solved by the invention] However, the offset gate type power MO8F with SOI structure
In ET, the underlying insulating film 2 is often formed of a thermal oxide film having high dielectric strength and cannot be made very thick.
In the above conventional structure, when a high voltage is applied to the drain diffusion region 7, as shown in FIG. An electric field E is generated, which causes avalanche breakdown (
AB) occurs and the drain breakdown voltage decreases. for that,
There has been a problem in that it has not been possible to obtain elements with a high withstand voltage that satisfactorily meet the demand. Furthermore, in the conventional structure described above, the current flowing between the source diffusion region 6 and the drain diffusion region 7 in the on state is determined by the resistance (on resistance) of the offset low concentration region 8, and there is also the problem that the drive current is limited. there were. Therefore, the present invention proposes an offset gate type MO with an SOI structure.
The purpose is to improve the drain breakdown voltage of 8FET and increase the on-current at the same time. [Means for Solving the Problem] The above problem is such that a semiconductor substrate, a base insulating film provided on the semiconductor substrate, a semiconductor layer provided on the base insulating film, and a phase separation between the semiconductor layer. an offset region formed in a space between the source diffusion region and the drain diffusion region, in contact with the drain diffusion region and spaced apart from the source diffusion region; A gate insulating film formed on the semiconductor layer, a gate electrode provided on the gate insulating film on a spaced part between the source diffusion region and the offset region, and directly below the drain diffusion region and the offset region. A semiconductor device according to the present invention selectively includes a lower drain electrode provided adjacently through an insulating film, and the lower drain electrode is electrically connected to the gate electrode via an inverter. be done. [Function] Fig. 1 is a schematic diagram for explaining the principle of the present invention, in which (a) is an off state, (b) is an on state, ■ is a semiconductor substrate, 2 is a base insulating film, and 3 is a semiconductor layer. , 4 is a gate insulating film, 7 is a drain diffusion region, 8 is an offset low concentration region, 9 is a drain lower electrode, and lO is an insulating film. According to the present invention, as shown in FIGS. 1(a) and (b),
A drain lower electrode 9 is provided adjacent to the lower part of the drain diffusion region 7 and the semiconductor layer 3 in the vicinity thereof with an insulating film 1O interposed therebetween,
In the OFF state of the MOSFET, as shown in FIG. 2(a), for example, the same VCC potential as the high potential VCC applied to the drain diffusion region 7 is applied to the drain lower electrode 9 via an inverter, and the drain diffusion region 7 and the apparent upper substrate (not the original substrate 1) to prevent avalanche breakdown of the drain junction due to the strong electric field between the drain and the substrate caused by this potential difference, and to Increases pressure resistance. Further, in the ON state of the FET, as shown in FIG. 2B, for example, V is applied to the drain diffusion region 7 to the lower drain electrode 9. A low potential Vss potential opposite to the C potential is applied via an inverter, and a strong electric field (E) is formed at the drain junction by the drain lower electrode 9 having a large potential difference with respect to the drain diffusion region 7. The electric field (E) causes avalanche breakdown (AB) at the drain junction. The carriers (+) or (-) generated thereby contribute to current flow between the source and the drain, thereby increasing the on-current (reducing the on-resistance). As described above, offset gate type MO8F with SOI structure
It is possible to improve the drain breakdown voltage of the ET and increase the on-current at the same time. [Example] The present invention will be specifically described below with reference to illustrated examples. FIG. 2 is a schematic diagram of one embodiment of the present invention, (a) is a circuit diagram, (bl is a side sectional view, and FIG. 3 is a schematic diagram of another embodiment of the present invention, (a) is a circuit diagram. Figure, (b) is a plan view, (C) is A
It is a sectional view taken along arrow A. Identical objects are designated by the same reference numerals throughout the plan. FIG. 2 shows an embodiment in which the present invention is applied to an amplifier circuit using a single (n) channel MO8. In the figure, l is a semiconductor substrate, 2 is a base oxide film made of 5iOz with a thickness of about 1 μm formed by thermal oxidation, 3A and 3B are semiconductor layers obtained by recrystallizing a polycrystalline silicon layer by laser beam irradiation, 3Afl, 3B , and 3B are a first n-type semiconductor layer and a second n-type semiconductor layer each having an impurity concentration of about l×10"am-' formed by selectively ion-implanting impurities.
- type semiconductor layer and p- type semiconductor layer, 4 is a gate oxide film with a thickness of about 500 to 100 OA formed by thermal oxidation, 5A, 5B+, 5B! 6A, 6B are gate electrodes made of polycrystalline silicon with high conductivity, and 6A, 6B are n+ type gate electrodes having an impurity concentration of about 10 to 10, respectively. The source diffusion region, 6B, is a 1ol layer formed in alignment with the sides of the gate electrode.
ll,,t6! (The p'' type source diffusion regions with an impurity concentration of about 1, ?A, , 7B are the 10th to
The n+ type drain diffusion region 7B, which has an impurity concentration of about 1olS-to!, is also formed apart from directly below the gate electrode. The p+ type drain diffusion regions 8A, 8B, each having an impurity concentration of approximately O, are formed with one end aligned with the gate electrode and the other end included within the drain diffusion region.
The n-type offset low concentration region 8B has an impurity concentration of about 2 to 3X10'' and is formed with one end aligned with the gate electrode and the other end included in the drain diffusion region. 9 is made of polycrystalline silicon imparted with high conductivity, a refractory metal, a refractory metal silicide, etc., and is selected below the drain diffusion region of the main transistor (T1) and its neighboring region. 10 is a CCV for insulating the lower drain electrode and the semiconductor layer.
Interlayer insulation film with a thickness of about 3000A by D-3to etc.
11 is a coating insulating film made of phosphosilicate glass (PSG) with a thickness of about 1 μm, 12 is a wiring contact window, 13Gl, 13Gx, 13G! is the gate wiring made of aluminum etc., 13s+, 13s2.13ss are the source wiring,
13D+, 13D, 13Ds are also drain wiring,
D is the input signal or its terminal, Deml is the output terminal, Vcc is the high potential power supply, ■, 8 is the ground power supply, Rt is the load resistance, T1 is the n-channel type main transistor for amplification, Tom is the n-channel type sub-transistor , T□ indicates a p-channel type side transistor INV, which is an inverter for applying a voltage to the lower drain electrode. In the above configuration, the input signal D Im for operating the main transistor (T1) is simultaneously input to the inverter INV for applying voltage to the lower drain electrode. And this signal D
I.M.

[0] That is, in the case of -oV, the main transistor (T1
) is that drain diffusion region off? A, Vc. Voltage is applied to the output terminal. , the VCC voltage is output to the drain lower electrode voltage applying inverter I.
The p-channel transistor (Tt-) of NV is turned on, the n-channel transistor (Tt, ) is turned off, and the drain lower electrode 9 of the main transistor (T1) is also connected to vcc.
A potential is applied. Therefore, the drain diffusion region of the main transistor (T1)? A
, and a drain lower electrode 9 disposed adjacent to the lower part thereof.
Since the potential difference between the drain diffusion region 7A and the drain diffusion region 7A becomes 0, a strong electric field is not formed near the junction of the drain diffusion region 7A, and avalanche breakdown of the junction is prevented, and a high drain breakdown voltage commensurate with the originally high junction breakdown voltage can be obtained. . Further, when the input signal D1 is [l], that is, +5V, the main transistor (T1) is turned on and a channel portion and an n-type offset low concentration region 8A are formed between its source diffusion region 6A and drain diffusion region 7A. On-current flows through the inverter (INV), but at this time, the p-channel transistor (T□) of the inverter (INV) is turned off, and the n-channel transistor (
T□) is turned on, VSS potential is applied to the drain lower electrode 9 of the main transistor (Tt), and VCC
A strong electric field is formed between the drain diffusion region 7A to which a potential is applied, the drain junction causes avalanche breakdown, and carriers (+) formed thereby flow into the source diffusion region 6A, increasing the on-current. , and the on-current increases accordingly compared to the conventional case of only channel current. In addition, in the above configuration, it was possible to increase the drain breakdown voltage of the element, which could conventionally only be obtained at about 150 V, to 200 V or more, and to increase the on-current, which was only about 30 mA, to about 60 mA. FIG. 3 is a circuit diagram (a), a plan view (b), and an A-A sectional view (C) showing another embodiment in which the present invention is applied to a CMOS inverter. In the figure, 101 is a semiconductor substrate, 102 is a base oxide film, 103A,
, 103B are n-type semiconductor layers, 103A, , 103
B, p-type semiconductor layer, 104, gate oxide film, 105
106A, 106B are n+ type source diffusion regions, 106A, 106B are p+ type source diffusion regions, and 107A are gate electrodes. , 107B are n+ type drain diffusion regions, 107A, .
107B, p+ type drain region, 108A, , 10
8B, n-type offset low concentration region, 108A, 1
08B is a p-type offset low concentration region, 109 is a drain lower electrode, llO is an interlayer insulating film, ll is a covering insulating film, 12 is a wiring contact window, 113 is a metal wiring, and D. is the input signal or its terminal, Deal is the output terminal, Vo
o is a high potential power supply, Vss is a ground power supply, T is an n-channel type main transistor that constitutes the main inverter for external control, Tlp is also a p-channel type main transistor, T2+
+ is an n-channel sub-transistor that constitutes a sub-inverter for applying voltage to the lower drain electrode, Tap is also a p-channel sub-transistor, INvl is a main inverter for external control, and INV is a sub-inverter for applying voltage to the lower drain electrode. It shows. In this configuration, when the OV signal is input to the input terminals (D, ,), Tlp of the main inverter (INVI) is turned on, TI+ is turned off, VCC potential is output to D611L, and the main inverter (INVI) is (INV,) n+ type drain diffusion region 107A and p- type semiconductor layer 103A,
A high voltage corresponding to VCC is applied to the junction between them, but at the same time, the sub-inverter (INV2) also operates in the same way, and the drain lower electrode 109 of the main inverter (INVI) also receives V. . Since a potential is applied, a high electric field directed toward the substrate is not formed at the drain junction, and
Avalanche breakdown of the junction is prevented and the above n+
Type drain region 107A. The junction breakdown voltage is improved. The above operation is similar when the p-channel transistor Tip of the main inverter (INV, ) is turned off. Further, when the signal [1], that is, +5V is input to D I++ and the n-channel type upper transistor Tea of the main inverter (INVI) is turned on, the n-channel type upper transistor Tea of the sub-inverter (INV2) is turned on by the same human input signal.
1 is also turned on and the main transistor T is connected to the lower drain electrode 109. n+ type drain diffusion region 107A. A VS11 potential equal to is applied, but at this time, in the same figure (
As is clear from b), by configuring the sub-inverter (INVt) to be smaller and smaller in capacity than the main inverter (INVI), the drain diffusion region 10 of the main transistor is
'ilA, the potential of the lower drain electrode 109 is switched faster than that of the lower drain electrode 109, thereby transiently causing avalanche breakdown at the junction of the drain region 107A, and causing the carriers generated there to gradually rise into a channel. The rise of the on-current is accelerated by adding the current to the current through the capacitor. The above effect is the same when the p-channel type soil transistor Tlp of the main inverter (rNVI) is turned on, and by promoting the rise of the on-current of each of the above transistors, the switching speed of the main inverter (INVI) is improved. The effect of being able to achieve this goal is obtained. [Effects of the Invention] As explained above, according to the present invention, the drain breakdown voltage of the SOI structure offset gate type MO8FET is improved,
Moreover, since it is possible to increase the on-current at the same time,
The driving ability and operating speed of a semiconductor IC using the above MOSFET can be increased.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a schematic diagram for explaining the principle of the present invention, in which (a) is an OFF state, (b) is an ON state, and FIG. 2 is a schematic diagram of an embodiment of the present invention. (a) is a circuit diagram, (b) is a side sectional view, FIG. 3 is a schematic diagram of another embodiment of the present invention, (a) is a circuit diagram, (b) is a plan view, and (C) is an A -A sectional view, FIG. 4 is a schematic side sectional view of the conventional structure, and FIG. 5 is a diagram showing problems of the conventional structure. In the figure, 1 is a semiconductor substrate, 2 is a base insulating film, 3 is a semiconductor layer, 4 is a gate insulating film, 7 is a drain diffusion region, 8 is an offset low concentration region, 9 is a drain lower electrode, and lO is an insulating film. ((W) OFF state (b) ON state Asahimoku A schematic diagram for explaining the principle of the invention (α) Circuit diagram (b) Side sectional view / 15 Schematic diagram of one embodiment of Hiroaki

Claims (1)

[Scope of Claims] A semiconductor substrate, a base insulating film provided on the semiconductor substrate, a semiconductor layer provided on the base insulating film, and a source diffusion region formed in a spaced manner in the semiconductor layer. and a drain diffusion region, an offset region formed in a space between the source diffusion region and the drain diffusion region, in contact with the drain diffusion region and spaced apart from the source diffusion region, and an offset region formed on the semiconductor layer. a gate insulating film, a gate electrode provided on the gate insulating film on a spaced part between the source diffusion region and the offset region, and an insulating film selectively provided directly below the drain diffusion region and the offset region. and a drain lower electrode provided adjacent to the drain lower electrode via an inverter, the drain lower electrode being electrically connected to the gate electrode via an inverter.