JPH03178235A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To eliminate the need for readjustment of a timing regulation circuit even when the change of different environmental condition is present on any of transmission and reception sides by providing an inverting circuit inverting the output of a timing signal generating circuit and sending the result to the reception section of other data transfer equipment provided opposite to the transmission section via a timing signal line. CONSTITUTION:A signal inverting the output of the timing signal generating circuit 2 is sent from the transmission side of the data transfer equipment having a transmission section and a reception section sending and receiving the data in time division multiplex via a timing signal line and a reception section of other data transfer equipment provided opposite to the transmission section receives the signal and generates n-kind of data latch timing signals of the same number as the degree of multiplex (n) from the signal. Thus, it is not required to measure actually the timing and to adjust it through the implementation of data transfer actually in order to obtain an optimum data latch timing signal 16 in matching with the transmission timing of the transmission section and even when the change of different environmental condition is present on any of transmission and reception sides, it is not required to readjust the timing regulation circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device, and more particularly to a data transfer device that transmits and receives data by time division multiplexing.

[Conventional technology]

As shown in the block diagram of FIG. 3, the conventional data transfer device has a configuration on the transmitting side that receives the data transfer timing signal 31 output from the timing signal generation circuit 21 and switches to time-division multiplex the data. A delay line circuit 22 that outputs a timing signal 32 is provided, and data registers 23-1, 23-2. . . . 23-n to gate circuits 24-1, 24-2, . By adding the switching timing signal 32 to 24-n, the data is time-division multiplexed and output to the transfer path 30 via the output buffer 25-1. The transfer timing signal 3 was output to the transfer path 30 via the output buffer 25-2. - In the configuration on the large input side, the input buffer 26-1 receives the time-division multiplexed data signal from the transfer path 30, and the input buffer 26-2 receives the data transfer timing signal 31.

The delay line circuit 27 that receives the data transfer timing signal 31 that is the output of the input buffer 26-2 creates sequentially delayed timing signals, and a timing adjustment circuit 28-1.28 for finely adjusting each output. -2.
~28-n. Timing adjustment circuit 28-1.
28-2. 28-n are data latch circuits 29-1, 29-2, . ~29-n. Data latch circuit 29-1.29-2°~29-
n latches individual data from sequential time-division multiplexed data signals.

FIG. 4 is an operational diagram of a conventional data transfer device.

FIG. 4(a) shows the transmitting side, and FIG. 4(b) shows the receiving side.

It is shown that the transmission side outputs a switching timing signal at every time t1. The delay line circuit 27 receives the data transfer timing signal 31 via the transfer path 30
is the optimum data latch timing signal 3 for each data latch circuit from this data transfer timing signal 31.
However, since only fixed time intervals can be set as the output of the delay line circuit 27, the timing adjustment circuits 28-1, 28-2. ~28-n is used to adjust the time slightly, and as shown in FIG. 4(b), the timing for each data latch circuit to latch data is determined at approximately the center time for each data. Obtain the rising edge of the signal.

[Problem to be solved by the invention]

The conventional data transfer device described above uses a timing adjustment circuit for each data latch circuit to slightly adjust the time, and in order to create the optimal data latch timing signal 33, the timing is adjusted by actually transferring data. This requires actual measurement and adjustment, and there is a problem in that the timing adjustment circuit must be readjusted if there is a change in environmental conditions on either the transmitting side or the receiving side.

An object of the present invention is to transmit a signal obtained by inverting the output of a timing signal generation circuit from the transmitting side of a data transfer device having a transmitting section and a receiving section that transmit and receive data by time division multiplexing via a timing signal line. Then, the receiving section of another data transfer device installed opposite to the transmitting section receives this signal, and creates n types of data latch timing signals, the same number as the multiplicity n, from this signal. In order to obtain the optimal data latch timing signal that matches the transmission timing of the To provide a data transfer device that does not require readjustment of a timing adjustment circuit even when conditions change.

[Means to solve the problem]

The data transfer device of the present invention has a transmitting section and a receiving section that transmit and receive data by time division multiplexing, and the transmitting section generates a data transfer timing signal synchronized with an internally generated tarok signal. an inverting circuit that inverts the output of the timing signal generating circuit and sends it to a receiving section of another data transfer device provided opposite to the transmitting section via a timing signal line; Number of digits n that is the same as the multiplicity n of the data
and a shift register having an integer m greater than and closest to the logarithm of the base 2 data multiplicity n for receiving the data transfer timing signal via the timing signal line. The configuration includes a counter having an output of the same number of bits as , and a decoder that receives the m-bit output of the counter and outputs n types of timing signals, the same number as the multiplicity n.

In the data transfer device of the present invention, the shift register provided in the transmitter has an output having the same number of bits as an integer m that is larger than the logarithm of the base 2 data multiplicity n and is closest to this number. It may be replaced with a counter and a decoder that receives the m-bit output of the counter and outputs n types of timing signals, the same number as the multiplicity n.

The data transfer device of the present invention includes a transmitting section and a receiving section that transmit and receive data by time division multiplexing, wherein the transmitting section generates a data transfer timing signal synchronized with an internally generated clock signal. an inverting circuit that inverts the output of the timing signal generating circuit and sends it to a receiving section of another data transfer device provided opposite to the transmitting section via a timing signal line; Receiving the transfer timing signal, a counter having an output of the same number of bits as an integer m that is larger than the logarithm of the data multiplicity n, which is base 2 and is closest to this number, and receiving the m-bit output of the counter. a decoder that outputs the same number of n types of timing signals as the multiplicity n; This configuration includes shift registers having a number n.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the configuration of the transmitting side, a clock signal output from a tarlock signal generating circuit 1 is converted into a data transfer timing signal 13 by a timing signal generating circuit 2, and is inputted to an n-bit shift register 3 and an inverting circuit 4. The shift register 3 that has received the data transfer timing signal 13 outputs a switching timing signal 14 for time-division multiplexing the data with a multiplicity of n. The data in the maximum n data registers 5-1.5-2° to 5-n are sequentially transferred to gate circuits 6-1°6-2.
6-n are time-division multiplexed by adding the switching timing signal 14 to the signals 6-n and output to the transfer path 8 via the output buffers 7--1. At the same time, the data transfer timing inversion signal 15, which is the output of the inversion circuit 4, is output to the transfer path 30 via the output buffer 7-2 in order to be used as a reference for the synchronization signal on the receiving side. - The configuration of the large input side is such that the input buffer 9-1 receives the time-division multiplexed data signal from the transfer path 8, and the data transfer timing inversion signal 15 is sent to the input buffer 9-2.
Receive at. The m-bit counter 10 that receives the data transfer timing inversion signal 15 output from the input buffer 9-2 repeatedly outputs the same pattern every time it counts n data transfer timing inversion signals 15. Here, m is an integer larger than the logarithm of n with base 2 and closest to this number. m-n decoder 1
1 decodes the output of the m-bit counter 10 and creates n types of data latch timing signals 16, the same number as the multiplicity n. Data latch circuit 12-1. L2-2. ~1
2-n receives the data latch timing signal 16;
How many pieces of data are latched from sequential time-division multiplexed data signals?

Next, the operation will be explained.

FIG. 2 is an operational diagram of a data transfer device according to an embodiment of the present invention. FIG. 2(a) shows the transmitting side, and FIG. 2(b) shows the receiving side.

Data register 5-1.5-2. ~5-n data is
The gate circuit 6- receives the switching timing signal 14 that is output every time the data transfer timing signal 13 rises.
1.6-2. ~6-n are sequentially sampled, and each data is sent out with a signal length t□. Since the data transfer timing inversion signal 15 is an inversion of the data transfer timing signal 13, the rising edge is the data transfer timing signal 13.
It lags behind by t2. These time division multiplexed data and data transfer timing inversion signal 5 are transferred to the transfer path 12.
On the receiving side, the time division multiplexed data and the data transfer timing inversion signal 15 are transmitted through the same transfer path 12.
Since the signals arrive via the m bit counter 10 and m
If the internal delay with the -n decoder 11 can be ignored, each data latch circuit will receive the data latch timing signal 16 approximately at the center of the data signal.

Therefore, when starting the service of this data transfer device, the data registers 5-1, 5-2. ~5-n and corresponding data latch circuits 12-1.12-2. .about.12-n, data will always be transferred in synchronization unless the device is stopped.

In addition, in the above-mentioned embodiment, the shift register provided in the transmitting section is replaced by an m-bit counter similar to that provided on the receiving side and an m-bit counter provided on the receiving side.
The same effect can be obtained even if the circuit is replaced with a circuit combining an n decoder.

Similarly, the same result can be obtained by providing a circuit that combines an m-bit counter and an m-n decoder in the transmitting section, and a shift register in place of the circuit that combines the m-bit counter and m-n decoder in the receiving section. effective.

〔Effect of the invention〕

As explained above, the present invention provides a timing signal line in which a signal obtained by inverting the output of a timing signal generation circuit is transmitted from the transmitting side of a data transfer device having a transmitting section and a receiving section that transmit and receive data by time division multiplexing. This signal is sent through a receiving unit of another data transfer device provided opposite to the transmitting unit, and n types of data latch timing signals, the same number as the multiplicity n, are created from this signal. This eliminates the need to actually perform data transfer, measure and adjust the timing in order to obtain the optimal data latch timing signal that matches the transmission timing of the transmitter, and allows both the transmitter and receiver to This has the effect of eliminating the need for readjustment of the timing adjustment circuit even when environmental conditions change.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an operational diagram of a data transfer device according to an embodiment of the present invention, FIG. 3 is a block diagram of a conventional data transfer device, and FIG. 4 is a conventional data transfer device. FIG. 2 is an operational diagram of the data transfer device of FIG. l...Clock signal generation circuit, 2...
Timing signal generation circuit, 3...shift register, 4...inversion circuit, 5-15-2. ~5-n
...Data register, 6-1.6-2. ~6-
n...Gate circuit, 7-1.7-2...
・Output buffer, 8... Transfer path, 9-1.9-
2...Input buffer, ○...m-bit counter, 11...m-n decoder, 12-
1, l2-2, ~12-n------
Data latch circuit, 13...Data transfer timing signal, 14...Switching timing signal, 1
5...Data transfer timing inversion signal, 16.
...Data latch timing signal.

Claims (1)

[Scope of Claims] 1. In a data transfer device having a transmitter and a receiver that transmit and receive data by time division multiplexing, the transmitter generates a data transfer timing signal synchronized with an internally generated clock signal. an inverting circuit that inverts the output of the timing signal generating circuit and sends it to a receiving section of another data transfer device provided opposite to the transmitting section via a timing signal line; a shift register having the same number of digits n as the data multiplicity n; and a decoder that receives the m-bit output of the counter and outputs n timing signals of the same number as the multiplicity n. A data transfer device characterized by: 2. The shift register provided in the transmitting section is configured by a counter having an output of the same number of bits as an integer m which is larger than the logarithm of the data multiplicity n which is base 2 and is closest to this number, and m bits of the counter. 2. The data transfer device according to claim 1, wherein the data transfer device is replaced with a decoder that receives the output and outputs n types of timing signals that are the same as the multiplicity n. 3. In a data transfer device having a transmitter and a receiver that transmit and receive data by time division multiplexing, the transmitter includes a timing signal generation circuit that generates a data transfer timing signal synchronized with an internally generated clock signal. , an inverting circuit that inverts the output of the timing signal generating circuit and sends it to a receiving section of another data transfer device provided opposite to the transmitting section via a timing signal line; and 2 receiving the data transfer timing signal. a counter that has an output with the same number of bits as the integer m that is larger than the logarithm of the multiplicity n of data with the base being and that is closest to this number; a decoder that outputs a timing signal, and the reception section includes a shift register that receives the data transfer timing signal via the timing signal line and has the same number of digits n as the multiplicity n of the data. A data transfer device characterized by: