JPH05268184A - Multiplex communication system - Google Patents

Abstract

PURPOSE:To prevent distortion in re-multiplex signal and deviation in the relation of location by synchronizing the sampling period of a distributer section with that of a multiplexer section. CONSTITUTION:In the multiplex communication system provided with a distribution section 1 receiving a multiplexing signal including plural multiplexed signals and sampling the multiplexing signal with a sampling signal whose period is synchronously with the multiplexing signal to distributingly output plural multiplexed signals and with a multiplexer section 2 sampling the plural multiplexed signals with a sampling signal of a prescribed period and outputting the multiplexing signal, the distribution section 1 outputs a synchronous signal synchronously with the received multiplexed signal to the multiplexer section 2 and the multiplexer section 2 synchronizes the sampling signal with the synchronous signal.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Prior Art (FIG. 5) Problem to be Solved by the Invention (FIG. 6) Means for Solving the Problem (FIG. 1) Action Example (a) First Implementation Description of Examples (FIGS. 2 to 3) (b) Description of Second Embodiment (FIG. 4) (c) Description of Other Embodiments

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributor for sampling a multiplexed signal and distributing and outputting the multiplexed signal, and a multiplexer for sampling the multiplexed signal and outputting the multiplexed signal. The present invention relates to a multiplex communication system having.

In multiplex communication, especially time division multiplex communication,
The form of multiplexing has become complicated.Multiple signals to be multiplexed are sampled at a certain cycle, their contents are multiplexed, and a multiplexing device that transmits the multiplexed signal and a multiplexed signal are received and multiplexed. There is a device provided with a relay device for receiving and distributing the multiplexed signal, re-multiplexing and transmitting the signal between the distributing device which restores the multiplexed signal at the same frequency as the time.

In such a relay device, synchronization between the distribution unit and the multiplexing unit is required.

[0005]

2. Description of the Related Art FIG. 5 is an explanatory diagram of a conventional technique. Figure 5
As shown in (A), in the relay device 4 that transmits the data of the mobile terminal device 5 to the host, the multiplexing unit 1b is provided in each mobile terminal device 5 to multiplex the clock, the data, and the status signal to generate an optical signal. Is transmitted to the relay device 4, and in the relay device 4, the received multiplexed signal is distributed by the distribution unit 1a, priority control is performed by the priority control unit 3, and the priority multiplexed signal is retransmitted by the multiplexing unit 2a. There is a system for multiplexing and transmitting to the next relay device 4.

In this way, the portable terminal device 5 and the relay device 4 can be connected by a serial optical line, and the relay devices 4 can be serially transferred, so that the connection can be simplified. That is, FIG.
As shown in (B), the relay device 4 having the distribution unit 1a and the multiplexing unit 2a is provided between the multiplexing unit 1b and the distribution unit 2b.

A multiplexer 1 for multiplexing the signals to be multiplexed.
The synchronization between b and the distribution unit 1a is maintained if the distribution unit 1a generates a sampling signal synchronized with the serial multiplexed signal and restores the multiplexed signal.

However, since the multiplexing unit 2a cannot control the synchronization by the multiplexed signal from the distributing unit 1a, it is synchronized with the internal free-running oscillation frequency when multiplexing the distributed signal (multiplexed signal). The sampling signal of the sampling period is set.

Each sampling period is obtained by dividing a clock supplied from another oscillation source and is within the error range of each oscillation source. However, the sampling period at the time of distribution and the sampling period at the time of re-multiplexing are asynchronous. It was.

[0010]

FIG. 6 is a diagram for explaining the problems of the prior art. However, the conventional technique has the following problems.

Since the sampling signal of the distributor and the sampling signal of the multiplexer are not synchronized, as shown in FIG. 6 (A), data distortion for the sampling period occurs,
Each time the signal is passed through the repeater, it is accumulated, and a distortion corresponding to one sampling occurs in the multiplexed signal (the multiplexed signal A2
Is sampled twice), which may cause a data error.

Therefore, the number of stages of the relay device is limited,
It is necessary to reduce the communication speed. As shown in FIG. 6B, when the sampling periods of all the multiplexed signals are not the same and the bit rates are different, the time slots of the multiplexed signals output from the distributor are The relative positional relationship of the data and the relative position of the data in the time slot of each multiplexed signal sampled by the multiplexing unit may be different (the positional relationship between the multiplexed signals A11 and B11 is deviated). ), The positional relationship between the data of each multiplexed signal is displaced.

Therefore, an object of the present invention is to provide a multiplex communication system capable of preventing the distortion of the remultiplexed signal and the shift of the positional relationship by synchronizing the sampling periods of the distributor and the multiplexer. To do.

[0014]

FIG. 1 shows the principle of the present invention. According to claim 1 of the present invention, a multiplexed signal including a plurality of multiplexed signals is input, sampling is performed with a sampling signal having a period synchronized with the multiplexed signals, and the plurality of multiplexed signals are distributed and output. Section 1 and the plurality of multiplexed signals are sampled with a sampling signal of a predetermined cycle,
In a multiplex communication system having a multiplexer 2 that outputs a multiplexed signal, the distributor 1 outputs a synchronization signal synchronized with the input multiplexed signal to the multiplexer 2, and the multiplexer 2
Is characterized in that the sampling signal is synchronized with the synchronization signal.

According to claim 2 of the present invention, in claim 1,
The synchronization signal has the same period as the bit length of the input multiplexed signal. According to a third aspect of the present invention, in the first aspect, the distribution unit 1 creates an output sampling signal of each distribution signal by the input multiplexed signal, and uses the cycle of each output sampling signal as the synchronization signal. It is characterized by outputting a phase synchronization signal reflecting the phase.

According to a fourth aspect of the present invention, in the first, second, or third aspect, frame information is provided in each frame of the multiplexed signal, and the distributing unit 1 uses the input multiplexed signal to generate the frame information. Is detected, the phase state of the divided signal synchronized with the synchronizing signal is initialized, and the multiplexed signal is output by the divided signal.

According to a fifth aspect of the present invention, in the fourth aspect,
The distribution unit 1 outputs the frame detection signal to the multiplexing unit 2, and the multiplexing unit 2 delays the frame detection signal to initialize the phase state of the sampling signal. ..

[0018]

According to the first aspect of the present invention, the distribution unit 1 outputs the synchronizing signal synchronized with the input multiplexed signal to the multiplexing unit 2,
The multiplexing unit 2 synchronizes the sampling signal for multiplexing with the synchronization signal, so that the multiplexing unit 2 samples the multiplexed signal in synchronization with the multiplexing signal input to the distribution unit 1. As a result, the multiplexed signal can be output, and the distortion and the positional shift of the re-multiplexed signal due to the sampling signal can be prevented.

According to the second aspect of the present invention, since the synchronizing signal has the same period as the bit length of the input multiplexed signal, the clock signal synchronized with the multiplexed signal of the distribution unit 1 can be used, which is easy. Can be realized.

In claim 3 of the present invention, the distribution unit 1 creates an output sampling signal of each distribution signal by the input multiplexed signal, and reflects the phase of the cycle of each output sampling signal as the synchronization signal. Since the output phase-synchronized signal is output, even if the sampling periods of the multiplexed signals are not the same (in the case of FIG. 6B), the data in the time slot of each multiplexed signal output from the distributor is output. It is possible to prevent the relative positional relationship from deviating from the relative positional relationship of the data in the time slot of each multiplexed signal sampled by the multiplexing unit.

According to a fourth aspect of the present invention, the distributor 1 detects frame information from the input multiplexed signal, initializes the phase state of the divided signal synchronized with the synchronizing signal, and outputs the divided signal. As a result, since the multiplexed signal is output, it is possible to accurately perform phase matching during distribution.

According to a fifth aspect of the present invention, the distribution unit 1 outputs the frame detection signal to the multiplexing unit 2, and the multiplexing unit 2 delays the frame detection signal to phase the sampling signal. Since the state is initialized, the multiplexing unit can also accurately perform phase matching at the time of multiplexing in synchronization with distribution.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (a) Description of the First Embodiment FIG. 2 is a block diagram of the distribution unit of the embodiment of the present invention, and FIG. 3 is a block diagram of the multiplexing unit of the embodiment of the present invention.

In FIG. 2, 10 is a PLL (Phase).
Lock Loop) unit to which the multiplexed signal is input, which has the same period as the bit length of the multiplexed signal and outputs the multiplexed synchronization signal synchronized with the change point of the multiplexed signal,
Reference numeral 12 denotes a serial / parallel conversion unit, which samples a multiplexed signal that is serial data with a multiplexed synchronization signal, converts the data in the time slot of the multiplexed signal into parallel data, and outputs the parallel data.

Reference numeral 13 is a frame detector, which is a serial / serial interface.
When a pattern of multiplexed frames (for example, "0" continues for 6 bits) is detected in the parallel data array from the parallel conversion unit 12, a frame detection signal is output, and 14 is a sampling signal generation unit. Yes, by inputting and dividing the multiplexed synchronization signal, a sampling signal of the multiplexed signal is generated and output.
Further, by initializing the frequency dividing circuit with the frame detection signal, the frame of the multiplexed signal and the phase of the sampling signal are synchronized.

Reference numerals 15-1 to 15-n are latch switching circuits, which switch the state of the serial / parallel converter 12 by a frame detection signal and switch the output of the latched contents by a sampling signal.

In FIG. 3, reference numeral 20 denotes a frame signal delay unit, which converts the frame detection signal from the distribution unit 1 into the distribution unit 1.
It is latched with the multiplexed synchronization signal from the above and outputs a delayed frame signal detection signal delayed by a fixed period of the multiplexed synchronization signal.

Reference numeral 21 denotes a sampling signal generator, which has the same configuration as the sampling signal generator 14 of FIG.
Inputs the multiplexed synchronization signal and divides it to generate and output sampling signals for each multiplexed signal. Also, by initializing the dividing circuit with the delayed frame detection signal, distribution is performed. As viewed from the sampling signal of the unit 1, the sampling signal is generated by delaying the multiplexing synchronization signal by a constant period.

Reference numerals 22-1 to 22-n each denote a latch circuit, which latches a multiplexed signal with a sampling signal and outputs the content thereof. Reference numeral 23 denotes a parallel / serial conversion section for a delay frame. Each latch circuit 22 by signal
The outputs of -1 to 22-n are latched, converted into serial data, and output as a multiplexed signal in synchronization with the multiplexed synchronization signal.

Next, the operation of this embodiment will be described with reference to FIG. The multiplexed signal input to the distributor 1 is
As shown in FIG. 1B, a 6-bit “0” is provided as frame information (frame pattern) in one multiplexed frame.
Are consecutive, the next "1" indicates the head flag, four multiplexed signals A, B, C, D are arranged, and the last "1" indicates the end flag.

The PLL unit 10 of the distribution unit 1 outputs a multiplexed synchronization signal having the same period as the bit length of the multiplexed signal from the multiplexed signal, and the serial / parallel conversion unit 12 multiplex-synchronizes the multiplexed signal. Parallel conversion is performed according to the signal.

When the frame detection unit 13 detects "0" of 6-bit continuous data from the parallel data, it outputs a frame detection signal, and the sampling signal generation unit 14 is initialized by the frame detection signal by the frequency dividing circuit. The multiplexed synchronizing signal is frequency-divided to create sampling signals for the latch circuits 15-1 to 15-n.

FIG. 1B shows the sampling signal of the first bit "1" next to the 6-bit "0" frame pattern signal, and the switching / latch circuits 15-1 to 15-1.
15-n latches the state of the multiplexed signal from the parallel / serial conversion unit 12 according to the frame detection signal,
Switch the latch contents by each sampling signal,
Output.

In the multiplexing unit 2, the frame detection signal is delayed by the frame signal delay unit 20 by the delay of the circuit operation,
The delayed frame signal is output and the sampling generator 21
Initializes the frequency divider circuit with the delayed frame signal and divides the multiplexed synchronization signal to generate sampling signals for each multiplexed signal.

Each of the latch circuits 22-1 to 22-n latches each multiplexed signal with the sampling signal and outputs the content thereof, and the parallel / serial conversion section 23 uses the delayed frame signal as each latch circuit 22-. The outputs 1 to 22-n are latched, converted into serial data by the multiplexed synchronizing signal, and output as a multiplexed signal.

As described above, since the distributing unit 1 sends the multiplexed synchronizing signal to the multiplexing unit 2, and the multiplexing unit 2 creates a sampling signal by the multiplexing synchronizing signal and samples the multiplexed signal. Sampling can be synchronized, and distortion of data due to sampling and deviation of positional relationship can be prevented.

Since the sampling circuit is initialized by the frame signal, the distributor 1 can be phase-matched with the multiplexed signal, and the multiplexer 2 can be phase-matched with the distributor 1.

(B) Description of the Second Embodiment FIG. 4 is an explanatory view of the second embodiment of the present invention. Figure 4 (A)
In, the same thing as shown in FIG. 2 to FIG.
The same symbols are used, and the configuration of the distribution unit 1 is the same as that of FIG. 2 and the configuration of the multiplexing unit 2 is the same as that of FIG.

In this embodiment, a sampling phase signal is sent from the distributor 1 as a synchronizing signal to the multiplexer 2. Next, the operation of this embodiment will be described with reference to FIG.

The multiplexed signal input to the distribution unit 1 is shown in FIG.
As shown in (B), 6 bits of “0” are consecutively provided as frame information (frame pattern) in one multiplexed frame, and the next “1” indicates a head flag. , A, B, C are arranged, and the last “1” indicates the end flag.

The PLL unit 10 of the distribution unit 1 outputs a multiplexed synchronization signal having the same period as the bit length of the multiplexed signal from this multiplexed signal, and the serial / parallel conversion unit 12 multiplex-synchronizes the multiplexed signal. Parallel conversion is performed according to the signal.

When the frame detector 13 detects "0" of 6 bits in a row from the parallel data, it outputs a frame detection signal, and the sampling signal generator 14 is initialized by the frequency detection circuit by the frequency dividing circuit. The multiplexed synchronizing signal is frequency-divided to create sampling signals for the latch circuits 15-1 to 15-n.

In FIG. 4B, since the data A has a 2-bit rate and the data B and C have a 1-bit rate, the sampling signals are as shown in A, B, and C, respectively. The switching / latch circuits 15-1 to 15-n latch the state of the multiplexed signal from the parallel / serial conversion unit 12 according to the frame detection signal, and switch the latch content according to each sampling signal and output it.

Of these sampling signals, sampling signals B and C reflecting the phase of each sampling signal are output to the multiplexing section 2 as sampling phase signals. In the multiplexing unit 2, the frame signal delay unit 20 delays the frame detection signal by the delay of the circuit operation and outputs the delayed frame signal, and the sampling generation unit 21 initializes the frequency dividing circuit with the delayed frame signal, A sampling signal of each multiplexed signal is generated in synchronization with the sampling phase signal.

Each of the latch circuits 22-1 to 22-n latches each multiplexed signal with the sampling signal and outputs the content thereof, and the parallel / serial conversion section 23 uses the delayed frame signal to latch each latch circuit 22-. The outputs 1 to 22-n are latched, converted into serial data by a synchronous clock, and output as a multiplexed signal.

As described above, the sampling phase signal is sent from the distributing section 1 to the multiplexing section 2, and the multiplexing section 2 creates a sampling signal from the sampling phase signal and samples the multiplexed signal. It is possible to prevent the distortion of data and the shift of the positional relationship due to sampling even for a multiplexed signal which is phase-synchronized and whose sampling period is not the same.

(C) Description of Other Embodiments In addition to the above embodiments, the present invention can be modified as follows. As the sync signal, the multiplexed sync signal and the sampling phase signal have been described as an example, but sync signals of other formats may be used.

Although the combination of one-stage distribution and multiplexing has been described, the present invention can be applied to a combination of multi-stage distribution and multiplexing. Although the present invention has been described with reference to the embodiments, various modifications are possible within the scope of the gist of the present invention, and these modifications are not excluded from the scope of the present invention.

[0049]

As described above, according to the present invention,
It has the following effects. The synchronizing signal synchronized with the multiplexed signal input by the distributing unit 1 is output to the multiplexing unit 2, and the multiplexing unit 2 synchronizes the sampling signal for multiplexing with the synchronizing signal.
In synchronization with the multiplexed signal input to the multiplexer 2, the multiplexer 2 can sample the multiplexed signal and output the multiplexed signal, prevent distortion of the remultiplexed signal due to the sampling signal, and generate data. It is possible to communicate at an allowable communication speed only with the magnitude of the distortion, and it is possible to eliminate the limitation on the number of stages of the relay device.

Further, since the multiplexing unit 2 can sample the multiplexed signal and output the multiplexed signal in synchronization with the multiplexed signal input to the distributing unit 1, the multiplexed signal and the multiplexed signal are re-multiplexed. It is possible to prevent the shift of the relative positional relationship with the digitized signal.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a distribution unit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a multiplexing unit according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

FIG. 6 is a diagram illustrating a problem of the conventional technique.

[Explanation of symbols]

 1 Distribution Unit 2 Multiplexing Unit 4 Relay Device 10 PLL Unit 12 Serial / Parallel Conversion Unit 13 Frame Detection Unit 14 Sampling Signal Generation Unit 15-1 to 15-n Switching / Latch Circuit 20 Frame Signal Delay Unit 21 Sampling Signal Generation Unit 22 -1 to 22-n Latch circuit 23 Parallel / serial conversion unit

Claims (5)

[Claims] 1. A distributor (1) for inputting a multiplexed signal including a plurality of multiplexed signals, sampling with a sampling signal having a period synchronized with the multiplexed signals, and distributing and outputting the plurality of multiplexed signals. ) And a multiplexing unit (2) for sampling the plurality of signals to be multiplexed with a sampling signal of a predetermined cycle and outputting the multiplexed signal, the distributing unit (1) A synchronizing signal synchronized with the input multiplexed signal is output to the multiplexing unit (2), and the multiplexing unit (2)
Is a multiplex communication system in which the sampling signal is synchronized with the synchronization signal. 2. The multiplex communication system according to claim 1, wherein the synchronization signal has the same period as the bit length of the input multiplexed signal. 3. The distribution unit (1) creates an output sampling signal of each distribution signal from the input multiplexed signal, and uses the phase synchronization that reflects the phase of the cycle of each output sampling signal as the synchronization signal. The multiple communication system according to claim 1, wherein a signal is output. 4. The frame information is provided for each frame of the multiplexed signal, and the distributor (1) detects the frame information from the input multiplexed signal and divides the frequency in synchronization with the synchronization signal. 4. The multiplex communication system according to claim 1, wherein the phase state of the signal is initialized and the multiplexed signal is output by the divided signal. 5. The distributing unit (1) outputs the frame detection signal to the multiplexing unit (2), and the multiplexing unit (2) delays the frame detection signal to output the sampling signal. The multiplex communication system according to claim 4, wherein the phase state is initialized.