JPH03179400A - Pcm sound source device - Google Patents

Abstract

PURPOSE:To accurately perform a looping process even by a pitch asynchronous system by using waveform data on a loop part start address as waveform data on a loop part end address and conforming the waveform data on the start address and end address to each other. CONSTITUTION:The waveform data S(s) stored in the address of a waveform memory 17 that start data SD indicates is read out and supplied to an interpolation control part 18, and the data after linear interpolation has its envelope processed by a multiplier 23 and is converted into an analog signal, which is supplied to a sound system 26 to generate its musical sound. When the area of a loop part is entered beyond an attack part, interpolation is carried out while it is considered that waveform data S(n) in a loop start point address LSPA is present at the position of an loop end point address LEPA, thereby correcting interpolated data corresponding to the distance between an integer part and the loop part end address. Consequently, the looping process can accurately be performed even by the pitch asynchronous system.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a PCM sound source device suitable for use in electronic musical instruments.

``Prior Art'' A PCM sound source has been developed that stores the peak values of musical tones as dental data over time and generates musical tone signals by reading and processing the stored values.

Among these PCM sound sources, there is an interpolation type pinch asynchronous sound source that can reduce the waveform memory size and does not require increasing the waveform memory address movement speed. Here, the sound source of this method will be explained.

FIG. 10(a) is a waveform diagram of the sound source. First, a sound source is sampled with a sampling pulse of a predetermined frequency (fs=fs1) shown in FIG. FIG. 5C shows waveform data stored in the waveform memory. Next, as shown in FIG. 10(d), the waveform data is interpolated (the figure shows linear interpolation), and the frequency fs,
Resample (fst≠fs) and read out the interpolated waveform data. That is, the frequency fs is different from the frequency fs.
A tentative sampling frequency conversion is performed by resampling by s2 (see pq in the same figure). Next, when fs is set to the same frequency as fs, a sound with a new pitch is generated (see figure (g)).

In this way, musical tones of any pitch can be obtained from a finite sample sequence, and there is an advantage that there is no need to create sampling pulses synchronized with the pitch of the musical tones.

By the way, in a PCM sound source, looping processing is performed for parts where the waveform repeats. This looping process is a process in which one cycle of the waveform is stored for a portion where the waveform repeats, and a repetitive waveform is generated by repeatedly reading out this portion.

First, looping processing in the pitch synchronization method will be explained.

For example, as shown in FIG. 11(A), when the original waveform (analog waveform) repeats, the sampling data by the pitch synchronization method becomes as shown in FIG. 11(0). In this case, only the waveform data of one predetermined period, for example, one period between point a and point b, is stored, and when the read address reaches point b, the waveform data is read out again by returning to point a. Make it. Also, between 81 points and 4 points, 32 points and 3 points
A similar effect can be obtained even if one period of waveform data between the two points is stored and read out repeatedly.

Next, pitch asynchronous looping will be explained.

Now, assuming that the sound source has the waveform shown in FIG. 12(A) and the sampling timing is as shown in FIG. 12(B), the sampled waveform data will be as shown in FIG. 12(C). The data obtained by linearly interpolating the waveform data in FIG. 3(C) is as shown in FIG. 2(D). here,
Let time t (x) in the figure be the starting point of repetition, and time t
Time t (x+T) after a loop section (repetition period T) has elapsed from (x) is the end point of the repetition. At this time,
The end points are sampling points (n+6) and (n+7)
Since the waveform data S(n+7) is located approximately in the middle or is not normally sampled, it is not possible to accurately interpolate the waveform data at the end point.

Therefore, if there is no waveform data S (n+7), looping processing cannot be performed accurately and waveform distortion occurs.

On the other hand, even if S (n+7) data is prepared, accurate looping processing cannot be performed unless adjustment with interpolated values in subsequent looping is taken into account. Because the pitch is asynchronous, S (n
The data at +7) is a different value from the data at S (n) (see Figure 12 (c)), and after performing interpolation using S (n+7), if we return to the starting point and perform interpolation again, An error occurs between the interpolated value in the first looping and the interpolated value in the second looping, and the error continues between the second and third looping, and between the third and fourth looping. This is because it will occur. This error causes waveform distortion, and furthermore, the manner in which the distortion occurs changes with each looping.

On the other hand, in the case of the pitch synchronization type, as shown in FIG. 11(b), the waveform data values at the starting point and the ending point are equal, and the above-mentioned disadvantage does not occur even if looping is performed. The present invention was made in view of the above circumstances, and an object of the present invention is to provide a pitch-synchronized PCM sound source device that can accurately perform looping processing and does not cause waveform distortion.

"Means for Solving the Problem" In order to solve the above problem, the invention described in claim (1) includes a waveform memory in which waveform data is stored at predetermined sampling intervals, and a Address data that updates the address data at intervals corresponding to the frequency of the sound, accesses the waveform data using an integer part of the address and the next integer of the integer part, and further outputs the decimal part of the address as interpolated data. a generation unit, and 2 accessed by the address data generation unit.
a data interpolation control unit that performs data interpolation based on the two waveform data and the interpolation data, and a loop unit is set in at least a part of the address space according to the address data,
a loop control section that controls the address data generation section so as to repeatedly access the loop section, and the data interpolation control section uses waveform data of the loop section start address as waveform data of the loop section end address. In the final section of the loop section, the waveform data accessed by the integer part immediately before the end address of the loop section and the waveform data of the start address are used, and the waveform data corresponding to the distance between the integer part and the end address is used. The present invention is characterized in that the interpolated data is corrected by using the interpolated data, thereby performing data interpolation.

Further, in the invention described in claim (2), the data interpolation control section uses waveform data of an end address as waveform data of a start address of the loop section, and in a first section of the loop section, the data interpolation control section and the waveform data accessed by the integer value immediately after the start address, and correct the interpolation data according to the distance between the integer value and the start address, thereby performing data interpolation. It is characterized by doing.

"Operation" In the inventions of claims 1 and 2, since each waveform data of the start address and end address of the loop section match, the interpolated value does not vary depending on the number of looping operations.

Further, in the invention described in claim 1, when the loop part end address includes a decimal part, the waveform data of the loop part start address can be used as the waveform data of this address. In the invention of
When the loop part start address includes a decimal part, the waveform data of the loop part end address can be used as the waveform data of this address.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

A: The basic principle of absolute perfection First, the basic principle of the embodiment will be explained.

First, set the address of the looping start point in the waveform memory as the loop start point address LSPA, and set the address of the looping end point as the loop end point address LE.
Let it be P.A. In the pitch asynchronous method, when the loop start point address LSPA is made to match the sampling point as shown in Figure 3 (B), the loop end point address LEPA does not match the sampling point as described above (see Figure 3 (B)). )reference). Moreover, since S (n-+-x) and S (n+x+l) are not sampled, interpolation cannot be performed between S(n+x-i) and the loop end point address LEPA. Therefore, in this embodiment, the waveform data of the loop start point address LSPA is used as the waveform data of the roof end point address LEPA, and the waveform data of the loop start point address LSPA is used as the waveform data of the roof end point address LEPA. The interpolation of S(n+x-1)
and S (n). this is,
If it is a periodic waveform, the loop end point address LE
This is based on the fact that the waveform data of PA is equal to the waveform data of loop start point address LS PA.

In this case, the distance between S(n+x-1,) and the loop end point address LEPA is different from the distance between normal sampling points, so S(n+x-1,)
1) and the loop end point address LEPA, the interpolated value is corrected.

By performing the interpolation processing as described above, the identity of each interpolated value in the looping processing is maintained, and waveform data without distortion can be obtained.

The above is the basic principle of this embodiment.

B. Configuration of Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. In the figure, reference numeral 1 denotes a keyboard consisting of a large number of keys, and key signals output from each key of the keyboard 1 are supplied to key press detection means 2. As shown in FIG. The pressed key detecting means 2 outputs a key code 'KC' indicating the key based on the key signal, and outputs ○\ as a key-on signal when a pressed key is detected. 3 is a frequency information generating section, which generates Fnanno. which is frequency information corresponding to the key code KC. This F number is input to an F number register 4.

Next, 5 is a control unit that controls each part of the device, including a CPU,
It consists of ROM, I10 board, etc. The control section 5 is configured to generate various control signals according to predetermined timings when the key-on signal KON is supplied.

8 is an adder, and one input terminal has an F number register 4.
The F number output by the selector 9 is supplied, and its output signal is supplied to one input terminal of the selector 9.

The selector 9 selects the signal ASEL output from the control unit 5 as “0”.
When the signal is "1", the 0th input terminal is selected, and when the signal is "l", the first input terminal is selected. A first input terminal of the selector 9 is supplied with start data SD from the control section 5. The start data SD is the read start address of waveform data and indicates the first address of the attack section. This start data SD is preset to various values depending on the tone color and the like. 10 is a subtracter, and the control unit 5 receives the signal R.
When D is output, the signal SD is subtracted from the output signal of the selector 9 and supplied to the shift register 11. Further, when the control section 5 does not output the signal RD, the output signal of the selector 9 passes through the subtracter 10 as it is and passes through the shift register 1.
1.

The shift register 11 receives a clock signal φ. , φ1. clock signal φ,
. , φ, are signals output at the timings shown in FIGS. Capture the signal being supplied at the rising edge of
Clock signal φ5. The signal captured at the rising edge of is output. The output signal of this shift register 11 is supplied to the other input terminal of the adder 8, and is added to the F number.

Next, 12 is a comparator, the loop end point address LEPA output from the control section 5 is supplied to the input terminal B, and the output signal of the adder 8 is supplied to the input terminal A. Then, when A>B, the signal CPI ("1" signal) is output, and when A>1nt(B), the signal CP2 ("BI signal") is output.
Output.

Here, A and B are the magnitudes of the signals supplied to the input terminals A and B, respectively, and 1nt(B) indicates the integer part of the signal supplied to the input terminal B. These signals CPU and CP2 are each supplied to the control section 5, and when the control section 5 is supplied with the signal CPI, it outputs the above-mentioned signal RD. Signal RD is a signal indicating the size of the loop, and the loop end point address LE
This signal indicates the difference between PA and the loop start point address LSPA.

Next, 16 is an adder that adds l'' to the integer part of the output signal of the soft register 11, and the output signal of this adder is supplied to the first input terminal of the selector 15. The input terminal is directly supplied with the integer part I of the output signal of the shift register 11. The selector 15 performs a selection operation in accordance with the clock signal φW.

In this case, the clock signal φW is output at the timing shown in FIG.
The first input terminal is selected when W is "L", and the O-th input terminal is selected when it is 0°.The output signal of this selector 15 is as follows.
The waveform data is supplied to the waveform memory 17 as address data, so that the waveform data stored in the waveform memory 17 is accessed by the positive part (2) and (1+1).

On the other hand, the decimal part i of the output signal of the shift register 11 is supplied to the O-th input terminal of the selector 19 and one input terminal of the multiplier 20 . The other input terminal of the multiplier 20 is supplied with correction data CD from the control section 5 . The correction data CD will be described later.

Further, the output signal of the multiplier 20 is supplied to the first input terminal of the selector 19. The selector 19 performs a selection operation in response to a signal BSEL supplied from the control unit 5, and selects the O-th input terminal when the signal BSEL is "O" and selects the first input terminal when the signal BSEL is "L". do. The output signal of this selector 19 is supplied to the interpolation control section 18 as interpolation coefficient data IPD. The interpolation control unit 18 receives the positive parts I and N output from the waveform memory 7.
Waveform data corresponding to =1), interpolation coefficient data IPD,
Interpolation is performed based on the signal BSEL and the signal BSEL. Here, the configuration of the interpolation control section 18 is shown in FIG.

In the figure, 30 is a selector, the O-th input terminal is supplied with waveform data read out from the waveform memory 17, and the first
The output signal of the LS register 31 is supplied to the input terminal. L
The value of the waveform data at the loop start point address LSP4 (hereinafter referred to as loop start point data LSPD) is written into the S register 31 when the key-on signal KON is generated. The selector 30 selects the first input terminal when the output signal of the AND gate 32 is "1", and selects the 0th input terminal when the output signal is "0". It is designed to perform logical product. A multiplier 33 multiplies the output signal of the selector 30 and the output signal of the selector 35, and its output signal is supplied to one input terminal of the adder 34. The interpolation coefficient data IPD is directly supplied to the first input terminal of the selector 35, and the interpolation coefficient data IPD is supplied after being bit-inverted by the bit inversion circuit 36 to the O-th input terminal.

The output signal of adder 34 is then provided to the input of output latch 38. The output latch 38 receives the clock signal φS
When umt (see FIG. 4 ( )) rises, the output signal of the adder 38 is latched. Also, adder 3
The output signal of 8 is provided to an accumulation latch 37. The accumulation latch 37 latches the output signal of the adder 34 when the clock signal φ5uIII rises, and is cleared every time the clear signal φclr (see FIG. 4(d)) rises. .

Next, 23 shown in FIG. 1 is a multiplier that multiplies the output signal of the interpolation control section 18 and the output signal of the envelope generation section 22. The envelope generating section 22 generates a predetermined envelope signal when the key-on No. 13 KON is supplied. By the multiplication process of the multiplier 23, an envelope is attached to the interpolated waveform data. The output signal of the multiplier 23 is converted into an analog signal by a D/A humbverter 25, and then supplied to a sound/stem 26 to generate a musical tone.

C. Operation of the Embodiment Next, the operation of this embodiment with the above configuration will be explained by dividing it into an attack section and a loop section (see FIG. 6).

■ Sound generation operation of the attack section First, when any key on the keyboard 1 is pressed, the key press detection circuit 2 detects whether the key is pressed and a key-on signal KON is generated.
is output. As a result, the control unit 5 outputs the signal ASE
L is set to a "1" signal to cause the selector 9 to select the first input terminal. As a result, start data SD or selector 9,
It is outputted via the subtracter 10 and the soft register 11, and its positive part (3) is supplied to the O-th input terminal of the selector 15. Here, when the clock signal φW is an "O" signal, (
Since the selector 15 selects the O-th input terminal (see FIG. 4(a)), the positive part I of the start data SD is supplied to the waveform memory 17 via the selector 15. As a result,
The waveform data S (s) stored at the address indicated by the positive part I of the start data SD is read out and supplied to the interpolation control section 18 . On the other hand, in the comparator 12, A<B
Therefore, the signals Cpl and cp2 are not output, and as a result, the signal BSEL becomes an "O" signal. When the signal BSEL is an "O" signal, the output signal of the AND gate 32 shown in FIG. 2 is always " When the output signal of the AND gate 32 is the "O" signal, the selector 30 selects the O-th input terminal, so the waveform data S (s) read from the waveform memory 17 is It is supplied to a multiplier 33 via a selector 30.

In addition, in the case of the signal BSEL or the "Q" signal, either the selector 19 shown in FIG. . Interpolated data IPD is supplied to multiplier 33 via selector 35 after being inverted via via 1 by bit inverting circuit 36 at the timing when clock signal φW is an “O” signal. If we invert this decimal part 1, the value becomes (1-i)
Therefore, in the multiplier 33, the start data S
Waveform data S (s) and (1-i
) or multiplied. This multiplication result (S <≦)・(1-i
)l is supplied to an accumulation latch 37 via an adder 34. The accumulation latch 37 has already been cleared by the clock signal φclr (see time t1 in FIG. 4(d)), and then, when the clock signal φ5Lffl+ rises at time t3 in FIG. 4(b), the above multiplication result is cleared. It is taken into the accumulation latch 37. As a result, the multiplication result (S
(S)·(1-1)) is supplied to the B input terminal of the adder 34.

Next, when the clock signal φW rises at time t4, the selector 15 shown in FIG. 1 selects the first input terminal. As a result, the output signal of the adder 16, that is, the value obtained by adding °'1'' to the start data SD, is determined by the selector 15.
The signal is supplied to the waveform memory 17 via the waveform memory 17. As a result, the waveform data S (s
+1) is read out. This waveform data S(s+1) is
The signal is supplied to a multiplier 33 via a selector 30 shown in FIG. At this time, since the clock signal φW is a "■" signal, the selector 35 selects the first input terminal, and the interpolation coefficient data IPD is supplied to the multiplier 33 via the selector 35. Since the interpolated data IPD in this case is the decimal part i of the start data SD, the calculation result in the multiplier 33 is S(s+1)·i. Then, this multiplication result is supplied to the input terminal of the adder 34, and the previous multiplication result +S (S)・(1iH
is added. This addition completes the linear interpolation, and when the linearly interpolated data or the clock signal φSIJmt rises (see time t5 in FIG. 4), the output
8 and output to the next stage. Here, it will be explained that linear interpolation is performed by the above calculation.

Now, the waveform data S (s) at the address indicating the positive part I of the start data SD, and the waveform data S (s) at the address where 1 is added to the positive part I of the start data SD.
S+1), respectively, as shown in FIG. Then, if the decimal part 1 of the start data SD is taken as shown, the waveform data S (s+
i) is expressed by the following formula.

=i-5(s+l)-i-3(s)
10S (s)・(1-i)S(s)+1-5(s+
1)... ・ (1) The first term on the right side of equation (1) is multiplied by the clock signal φW.
is an operation performed by the multiplier 33 when is “○”,
The second term multiplication is an operation performed by the multiplier 33 when the clock signal φW is "1". Therefore, when the respective multiplication results are added together in the adder 34, the result becomes equivalent to the right side of equation (1), which means that linear interpolation has been performed.

Next, the data after linear interpolation is outputted from the output lanochi 38, and subjected to engelofing processing by the multiplier 23.
Thereafter, the signal is converted into an analog signal by the D/A converter 25, and then emitted as a musical tone by the Saranton stem 26.

On the other hand, the start data SD output from the frequency register 11 is supplied to the other input terminal of the adder 8 shown in FIG. 1, and is added to the F number output from the F number register 4. At this time, the signal ASEL output from the control section 5 is O
” signal, and as a result, the selector 9 selects the ○th input terminal. As a result, the addition result in the adder 8 is sent to the selector 9, the subtracter 10, and the register 11.
Output via . Then, the same waveform data reading and linear interpolation processing as in the above case is performed for the integer part I and the decimal part i. Also, /futore/sta1
The output signal of 1 is supplied to the other input terminal of the adder 8, and thereafter the F numbers are sequentially accumulated through this loop. Therefore, waveform data reading and interpolation processing are performed sequentially for the integer part ■ and the fractional part i of the data that are accumulated sequentially, and as a result, the waveform data of the attack part is created by the interpolation processing. . Each waveform data of this attack section is emitted as a musical tone after being subjected to enherobe processing as described above.

Sound generation operation of C loop section Next, the sound generation operation of the loop section will be explained.

As the F numbers are sequentially accumulated for the start data SD as described above, the read address of the waveform memory 17 goes beyond the attack area shown in FIG. 6 and enters the loop area. Then, read the waveform data of the loop section,
The interpolation processing is basically performed in the same manner as in the case of the acrylic and aliasing parts.

However, as the accumulation of F numbers progresses, the output signal of the frequency register 11 becomes waveform data S (n-+
-x-1) and the loop end point address LEPA (hereinafter referred to as a specific interpolation section), the processing contents differ from the above-mentioned processing. This process will be explained below.

First, when the output signal of the adder 8 enters a specific interpolation interval, A>1nt(B) in the comparator 12. Adder 12
The loop end point address LEPA is at the B input end of
is supplied, 1nt(B) ends up being the integer part of the loop endpoint address LEPA. As can be seen from FIG. 3(A), the integer part of this loop end point address LEPA is the address value of the waveform data (S+x-1) and is the starting point of the specific section. And A
>1 nt (B), the comparator 12 outputs the signal CP2, which causes the control unit 5 to set the signal BSEL to "1" and output the correction data CD. Here, the correction data CD is data set so that its reciprocal 1/CD becomes the decimal part of the loop end point address LEPA (see FIG. 3(c)).

When the signal BSEL becomes the "L" signal, the selector 19 shown in FIG.
A multiplication value 1·CD of the decimal part of the output signal of the star 11 and the correction data CD is output as interpolation coefficient data IPD.

Furthermore, when the signal BSEL becomes a 1/2 signal, a "1" signal is supplied to one input terminal of the AND gate 132 shown in FIG. Uniquely determined. Therefore, Kuro.

When the output signal φW is a “°0” signal, the selector 30 selects the O-th input terminal, and the waveform data read from the waveform memory 17 is supplied to the multiplier 33.

At this time, since the accumulated value of the F number is within the specific interpolation interval, the waveform data accessed by the integer value T is waveform data 3 (n+x
-1). Further, at this time, since the selector 35 selects the O-th input terminal, the multiplier 33 multiplies the bit inverted value of 1-CD by the waveform data S(n+x-1). Therefore, the multiplication result of the multiplier 33 is (1-i
−cD)・S (n+x−1). This multiplication result is taken into the accumulation latch 37 through the input terminal and output terminal of the adder 34 in sequence, and is supplied to the B input terminal of the adder 34. Next, when the black/7 signal φW rises (see time t4 in FIG. 4(a)), the ant gate 32 outputs the "l" signal and the selector 30 selects the first input terminal. As a result, the first waveform data of the loop section stored in the LS register 31, ie, the waveform data S(n), is supplied to the multiplier 33. Also, whether the clock signal φW or “
1" signal, the selector 35 selects the first input terminal, so the interpolation coefficient data IPD is directly supplied to the multiplier 33. As a result, the multiplication result in the multiplier 33 is S
(n) ・1-CD. This multiplication result is supplied to the A input terminal of the adder 34, and is added to the previous multiplication result that has been supplied to the B input terminal. Therefore, in the adder 34, S (n+x-1) · (1-
i-CD) ・CD+S(su)・1-cD is performed. Here, the meaning of this calculation will be explained.

First, in this embodiment, as described above, it is assumed that the waveform data S(n) of the loop start point address LSPA is located at the position of the loop end point address LEPA, and interpolation of a specific interpolation section is performed. . By the way, the interval between the specific interpolation sections is 1/CD, as shown in FIG. 3(C), which is shorter than the intervals between the other sections.

Therefore, the decimal part 1 needs to be converted into a ratio to the length of the section, and it may be necessary to divide it by the length of the section (1/CD). As a result, the decimal part i is multiplied by CD, which is equivalent to treating the length of the specific interpolation section as "1" like other sections. This enlarged state is shown in FIG. In FIG. 7, the loop end point address LEPA is shifted to the right to become LEPA-, and the length of the section is set to 1''. Correspondingly, if the value of the decimal part i is multiplied by CD, it can be seen that the above-mentioned equation (1) can be applied to the expanded section and interpolation can be performed. That is, i on the right side of equation (1) may be replaced with i.CD, waveform data S (s) may be replaced with S(n+X-1), and waveform data S (S+1) may be replaced with S (n). The right side after this replacement corresponds to the operation of the adder 34,
It can be seen that appropriate interpolation was performed.

The addition result of the adder 34 is the clock signal φ5I
At the rising edge of Jffh (see FIG. 4(C)), the signal is taken into the output latch 38 and output to the subsequent circuit.

Next, when the F numbers are accumulated in the adder 8 shown in FIG. 1, the same processing as described above is performed on this accumulated value. However, in the specific interpolation period, as can be seen from FIG.
(n+x-1) indicates the stored address. Then, when the clock signal φW becomes "1", the selector 30 shown in FIG.
In the specific interpolation interval, interpolation is performed between the waveform data S (n↓X-1) and S (n) regardless of fluctuations in the F-number cumulative value. What influences the interpolation is the decimal part of the F number accumulated value, that is, the decimal part 1 of the output signal of the nft register 11, and the interpolated value according to the fluctuation of the decimal part l accompanying the accumulation of F nuts is the interpolation control. The parts 18 are outputted in the given order.

Then, when the F number cumulative value becomes even larger, the value exceeds the area of the loop portion (see FIG. 6).

As a result, in the comparator 12 shown in FIG.
! :, and the signal CPl is output from the comparator 12 to the control section 5. When the control unit 5 is supplied with the signal CP, it outputs the signal R.
D is supplied to the subtractor lO, resulting in subtraction by the subtractor 10. Here, since the signal RD is a signal indicating the size of the loop, when subtraction is performed by the subtractor l○, the loop size will be calculated from an address slightly exceeding the loop end point address LEPA. Become. Therefore, the calculated value is the start address of the loop section, that is, the loop start point address LSE
, A (see FIG. 6). In this case, the subtraction value or the loop start point address LSEA
Even if the waveform data S of the loop start point address LSEA does not completely match, the interpolation control unit 18
Since interpolation processing is performed between (n) and the waveform data in the subtracted value, no inconvenience occurs. Thereafter, the F number is sequentially accumulated in the subtracted value, and the same waveform data reading and interpolation as described above are performed for each accumulated value. Then, the accumulated value or the loop end point address LEP
If it exceeds A, subtraction is performed by the subtracter 10, and the loop returns to the vicinity of the loop start point address LSEA again. In this way, thereafter, waveform data is repeatedly read and interpolated within the loop section.

In the above operation, since the waveform data of the loop end point address LEPA is matched with the waveform data S (n) of the loop start point address LSEA, there is no possibility that an error will occur in the interpolated value depending on the number of looping operations.

D: Modification of the embodiment In the embodiment described above, the loop start point atres L
Was this an example where SEA does not have a decimal part I and the loop et point address LEPA has a decimal part 1?
(See Figures (a) and (b)), and conversely, Figures 8 (a) and (b).
Loop start point address LS as shown in b)
Even if EA has a decimal part I and the loop end point address LEPA does not have a decimal part 1, the same processing as in the above embodiment can be performed. However, in this case, as shown in FIG. 3B, the waveform data of the loop end point address LEPA is placed at the address position of the loop start point address LSPA, and interpolation is performed using this data. Therefore, it is necessary to configure the interpolation control section 18 as shown in FIG. 9. The difference between the circuit shown in FIG. 9 and the circuit shown in FIG. 8 is that
In place of the LS register 31, an LE register 0 is provided to store the waveform data at the loop end point address LEPA, and the clock signal φW is supplied to one input terminal of the AND gate 32 via the inverter 41. be. In addition, the signal BSE shown in FIG.
L is configured to become a "1pa signal" in the specific interpolation section shown in FIG. 8(C).

According to the above configuration, interpolation is performed between waveform data S (n+x) and waveform data 5 (n-1-1) in the specific interpolation section shown in FIG. 8(c). The section width of the specific interpolation section is corrected using the correction data CD as in the previous embodiment, so the processing contents are as shown in FIG.

Therefore, the circuit shown in FIG. 9 can also provide the same effects as the above-described embodiments.

"Effect of the invention" As explained above, according to the invention described in claim 1,
A waveform memory that stores waveform data at predetermined sampling intervals and address data at intervals corresponding to the frequency of the sound to be generated are updated, and the waveform is updated using the integer part of the address and the next integer after the integer part. an address data generation unit that accesses data and further outputs the fractional part of the address as interpolation data; and a data interpolation unit that performs data interpolation based on the two waveform data accessed by the address data generation unit and the interpolation data. a control unit; and a loop control unit that sets a loop unit in at least a part of the address space by the address stator and controls the address data generation unit so as to repeatedly access the loop unit, and the data interpolation unit The control unit uses the waveform data of the loop part start address as the waveform data of the loop part end address, and in the final section of the loop part, the waveform data accessed by the integer part immediately before the loop part end address and the loop part start address. The interpolation data is corrected in accordance with the distance between the integer part and the loop part end address, and data interpolation is performed thereby. In the invention described above, the data interpolation control unit uses waveform data of a loop part end address as waveform data of a start address of the loop part, and uses waveform data of a loop part end address and waveform data of a loop part end address in the first section of the loop part. Using the waveform data accessed by the integer value immediately after the loop part start address, and correcting the interpolated data according to the distance between the integer value and the loop part start address, data interpolation is performed. As a result, even though it is a pinch asynchronous method, looping processing can be performed accurately, and there is an advantage that waveform distortion does not occur.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing the arrangement of the interpolation control section in the embodiment, and Fig. 3 is the boundary and waveform of the loop section in the embodiment. 4 is a conceptual diagram showing the positional relationship of data, FIG. 4 is a timing chart showing the timing of the clock signal in the same embodiment, FIG. 5 is an explanatory diagram for explaining the linear interpolation process in the same embodiment, and FIG. 6 is the same A waveform diagram showing the at-tank part and the loop part of the readout waveform in the embodiment, FIG. 7 is an explanatory diagram for explaining correction processing of a specific interpolation interval in the embodiment, and FIG. 8 is a modified example of the embodiment. Conceptual diagram showing the positional relationship between the boundary of the loop part and the waveform data in
The figure is a block diagram showing an example of the configuration of the interpolation control section 18 in the modified example, FIG. 10 is a waveform diagram for explaining the sound generation principle of the pitch asynchronous method, and FIG. 11 is a waveform diagram for explaining the sound generation principle of the pitch asynchronous method. FIG. 12 is a waveform diagram for explaining the conventional looping process in the pitch asynchronous system. 3...Frequency information generation section, 4...F number register, 8...Adder, 9...Selector, 10...Subtractor, 11... ...Shift register, 15...Selector, 16-...Adder, 19...Selector (3.4, 8, 9, 1
0. LL 15, 16, 19 are address data generation sections), 5...control section (loop control section), 17...
...Waveform memory, 18...Interpolation control section.

Claims (2)

[Claims] (1) A waveform memory that stores waveform data at predetermined sampling intervals, updates address data at intervals corresponding to the frequency of the sound to be produced, and also updates the integer part of the address and the next integer after the integer part. access the waveform data by
further comprising: an address data generation section that outputs a fractional part of the address as interpolation data; a data interpolation control section that performs data interpolation based on the two waveform data accessed by the address data generation section and the interpolation data; a loop control unit that controls the address data generation unit to set a loop unit in at least a part of an address space based on address data and repeatedly access the loop unit; The waveform data of the loop part start address is used as the waveform data of the part end address, and in the final section of the loop part, the waveform data accessed by the integer part immediately before the loop part end address and the waveform data of the loop part start address are used. and correcting the interpolation data in accordance with the distance between the integer part and the loop part end address, thereby performing data interpolation. (2) A waveform memory that stores waveform data at predetermined sampling intervals, updates address data at intervals corresponding to the frequency of the sound to be produced, and also updates the integer part of the address and the next integer after the integer part. access the waveform data by
further comprising: an address data generation section that outputs a fractional part of the address as interpolation data; a data interpolation control section that performs data interpolation based on the two waveform data accessed by the address data generation section and the interpolation data; a loop control unit that controls the address data generation unit to set a loop unit in at least a part of an address space based on address data and repeatedly access the loop unit; The waveform data of the loop part end address is used as the waveform data of the start address of the loop part, and in the first section of the loop part, the waveform data of the loop part end address and the waveform data accessed by the integer value immediately after the loop part start address are used. A PCM sound source device characterized in that the interpolation data is corrected in accordance with the distance between the integer value and the loop part start address, thereby performing data interpolation.