JPH0318055A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the capacity of stacked capacitor cells by forming a hole or a groove on a field oxide film of a part in contact with the first electrode of the capacitor. CONSTITUTION:A capacitor of a capacitor type memory cell has source or drain regions 12a, 12b of a transistor of the cell, a first electrode 6 extended on adjacent word lines 4a, 4b on a gate of a transistor through an insulating film 5 in contact with a field oxide film 2, a dielectric film 7 formed on the electrode 6, and a second electrode 8 on the film 7. A hole or a groove 14 is formed on the film 2 at the part in contact with the electrode 6 of the cell. Accordingly, stacked capacitor cells can be increased in an actual area without increasing the area as seen in a plane. Thus, the capacity of the stacked capacitor cells can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a stacked capacitor type cell.

2. Description of the Related Art In recent years, the capacity of semiconductor memory devices has been increased due to miniaturization and higher density integration of semiconductor devices.

Therefore, stacked capacitor type cells are currently being proposed.

FIG. 2 shows a cross-sectional view of a dynamic semiconductor device having a conventional star-socket capacitor type cell. In FIG. 2, 1 is a silicon substrate, 2 is a field oxide film,
3& and 3b are gate oxide films, 4& and 4b are word lines made of the first layer polycrystalline silicon film, 13 is a side wall, and 12a and 12b are source casings or drains.
7 is an n-type diffusion region; 6 is an interlayer insulating film; 6 is a first electrode of a stacked capacitor consisting of a second layer of polycrystalline silicon film;
1 is a capacitive insulating film, 8 is a second electrode of a stacked capacitor consisting of a third layer of polycrystalline silicon film, 9 is an insulating film between eyebrows, 1
0 is an insulating film between the eyebrows made of boron phosphosilicate glass, 11
indicates a bit line made of a polycide film.

Problems to be Solved by the Invention The semiconductor device having the stacked capacitor type memory cell described above achieves a large capacitance of the memory cell capacitor by effectively utilizing the space on adjacent word lines, so it is possible to achieve a short channel. Malfunctions due to hot electrons and hot holes caused by
It goes without saying that if a larger capacity can be achieved, it will be even more advantageous to achieve higher density and higher integration.

The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device that can realize an even larger capacity.

Means for Solving the Problems In order to achieve the above object, the present invention provides a plurality of hood lines, a plurality of bit lines arranged to intersect with the plurality of hood lines, and a combination of the word line and the focus line. It has one transistor and one capacitor type memory cell provided at the intersection,
The capacitor of the memory cell is connected to a first electrode that is in contact with the source or drain/region of the transistor of the memory cell and a field oxide film, and that extends over a gate portion of the transistor and an adjacent word line through an insulating film. The field oxide film is composed of a dielectric film formed on one electrode and a second electrode on the dielectric film, and a hole or groove is formed in the field oxide film at a portion in contact with the first electrode of the memory cell. This is a semiconductor device characterized by:

Effect: According to the means described above, holes or grooves can be formed in the field oxide film at the portion in contact with the first electrode of the stacked capacitor without enlarging the area of the stacked capacitor cell when viewed from the plane. The actual area of the stacked capacitor cell can be increased, and at the same time, the capacity of the stacked capacitor cell can be increased.

Embodiment FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention.

In FIG. 1, 1 is a silicon substrate, 2 is a field oxide film, 3a and 3b are gate oxide films, 42L and 4b are word lines made of the first layer of polycrystalline silicon film, 6 is an insulating film between the eyebrows, and 6 is a two-layer The first electrode of the stacked capacitor made of a polycrystalline silicon film, 7 the capacitive insulating film, and the third electrode 8 of the stacked capacitor made of a polycrystalline silicon film.
9 is a glabellar insulating film, 1o is a glabellar insulating film made of poronphosphosilicate glass, 11 is a bit line made of a polycide film, 12& and 12b are n+ type diffusion regions to be sources or drains, 13 is a side wall, and 14 is an electrode. A hole or trench formed in the field oxide is shown. At this time, by setting the depth of the groove or hole to 5Q nm to 1 μm, the step of the stacked cell is increased and the cell area is increased.

By using the above method, it is possible to substantially increase the area and the capacity of the stacked capacitor without increasing the planar area.

Effects of the Invention By using the semiconductor device according to the present invention, it is possible to substantially increase the area and capacity of a stacked capacitor without increasing its planar area.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device. 1... Silicon substrate, 2... Field oxide film, 3a, 3b... Gate oxide film, +
a, 4b... Word line, 6... Interlayer insulating film, 6... First electrode of stacked capacitor, 7... Capacitive insulating film, 8...Second electrode of stacked capacitor, 9...Interlayer insulating film, 10...Interlayer insulating film, 11...Bit line, 121L, 12b...Diffusion layer region, 1
3... Sidewall, 14... Hole or groove formed on the field oxide film.

Claims (2)

[Claims] (1) A plurality of word lines, a plurality of bit lines arranged to intersect with the plural word lines, and one transistor and one capacitor type memory cell provided at the intersection of the word lines and the bit lines. The capacitor of the memory cell has a first electrode that is in contact with the source or drain region of the transistor of the memory cell and the field oxide film, and extends over the gate portion of the transistor and the adjacent word line via an insulating film. and a dielectric film provided on the first electrode and a second electrode on the dielectric film, and a hole or groove is formed in the field oxide film at a portion in contact with the first electrode of the memory cell. A semiconductor device characterized in that: is formed. (2) The semiconductor device according to claim 1, wherein the depth of the hole or groove is in the range of 50 nm to 1 μm.