JPH03180776A - Logic circuit provided with self-diagnostic function - Google Patents

Abstract

PURPOSE:To easily decide the fault part of logic circuit with a simple circuit constitution by providing a 1st selecting means common to each parial logic circuit, input pattern storing means, expected value pattern storing means and comparison means. CONSTITUTION:When a self-diagnosis is made, the input patterns for test are supplied to the logic circuit 12 from a ROM 14 through a selector 10 and, for example, the output data of logic circuit 12c are supplied to a comparator 18. The data and the expected value patterns from a ROM 16A are compared by a comparator 18, and when the decision is made as noncoincident, new selecting signal is supplied to a selector 20 by an FF 22 through an AND gate 28 and also an additional address signal corresponding to this selecting signal is supplied to the ROM 16A. With this procedure, the output data of other logic circuits 12b, 12a and the expected value patterns corresponding thereto are compared by the comparator 18, and when both data are noncoincident, such a process is further repeated. Consequently, the fault part of circuit 12 can be detected with the simple circuit constitution in accordance with the condition of FF 22 or ROM 16A.

Description

[Detailed description of the invention]

[[Required] With regard to logic circuits with self-diagnosis functions, the purpose is to simplify the configuration and make it easy to know which part of the logic circuit is malfunctioning. a first logic circuit for selectively supplying normal input data to the logic circuit and the input pattern to the logic circuit; a selection means; an expected value pattern storage means storing an expected value pattern to be output when the partial logic circuit operates normally in response to the input pattern to the logic circuit; the input pattern storage means; and the expected value. address generation means for supplying an address signal to the pattern storage means so that the two patterns correspond; a second selection hand for selecting one of the outputs of the partial logic circuit in response to the selection signal; a comparison means for determining whether the data selected by the second selection means and the data from the expected value pattern storage means match; and when the comparison means determines that they do not match;
A switching control means for supplying a new selection signal to the second selection means and for supplying an additional address signal corresponding to the selection signal to the expected value pattern storage means.

[Industrial application field]

The present invention relates to a logic circuit equipped with a self-diagnosis function that tests whether the logic circuit operates normally and points out the location of a failure.

[Conventional technology]

FIG. 3 shows the principle configuration of a conventional logic circuit with a self-diagnosis function. This logic circuit with a self-diagnosis function has a normal mode and a self-diagnosis mode. In the normal mode, input data is supplied to the logic circuit 12 via the selector 10, and in the self-diagnosis mode, input data is input from the input pattern ROM 14 for testing. The pattern is supplied to the logic circuit 12 via the selector 1o. In the self-diagnosis mode, the output data of the logic circuit 12 and the expected value pattern from the expected value pattern ROM 16 are compared by the comparator 18, and if the two data do not match, the comparator 1
A failure signal is output from 8. When performing self-diagnosis on multiple logic circuits 12,
Conventionally, a configuration similar to that shown in FIG. 3 was connected in series or in parallel, and a failure signal from each comparator 18 was supplied to an OR gate (Japanese Patent Laid-Open No. 62-188980, Japanese Patent Laid-open No. 188980, 62-196863). Since the self-diagnosis function is not used during normal operation, its circuit scale must be kept as small as possible.

[Problem to be solved by the invention]

However, for each logic circuit, a selector 10, an input pattern R
Since the OM, expected value pattern ROM 16, and comparator 18 were provided and connected to each other, the configuration became complicated as the number of logic circuits increased. Furthermore, even if a failure signal is output from the OR circuit, it is unclear from which logic circuit the failure was detected, and the potential of each signal line supplied to the OR circuit is measured to determine which logic circuit has failed. I needed to find out if it was. SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide a logic circuit with a self-diagnosis function that has a simple configuration and can easily determine which part of the logic circuit is malfunctioning.

[Means to solve the problem]

FIG. 1 shows the basic configuration of a logic circuit with a self-diagnosis function according to the present invention. In the figure, 1 is a logic circuit, which is composed of a plurality of partial logic circuits, for example, four partial logic circuits 1a to 1d. The connection between the partial logic circuits 1a to 1d may be serial, parallel, or a combination of both. Reference numeral 2 denotes an input pattern storage means in which test input patterns to be supplied to the logic circuit 1 are stored. 3 is a first selection means, which selectively supplies normal input data to the logic circuit 1 and the input pattern to the logic circuit 1; 4 is an expected value pattern storage means, which is a partial logic circuit 1a.
For the input pattern to the logic circuit 1 when the partial logic circuits 1a to 1d operate normally, an expected value pattern to be output when the partial logic circuits 1a to 1d operate normally is stored. 5 is an address generation means, and input pattern storage means 2
and an address signal is supplied to the expected value pattern storage means 4 so that both patterns correspond to each other. A second selection means 6 selects one of the outputs of the partial logic circuits 1a to 1d in response to a selection signal. 7 is a comparison means, which determines whether the data selected by the second selection means 6 and the data from the expected value pattern memory child actor 4 match. Reference numeral 8 denotes a switching control means, which supplies a new selection signal to the second selection means 6 and adds a new selection signal to the expected value pattern storage means 4 in accordance with the selection signal when the comparison means 7 determines that there is no match. address signal.

[Effect]

At the time of self-diagnosis, the test input pattern from the input pattern storage means 2 is supplied to the logic circuit 1 via the first selection means 3, and the output data of any of the partial logic circuits 1a to 1d is supplied to the logic circuit 1 via the second selection means 6. It is supplied to comparison means 7. The comparison means 7 compares this data with the expected value pattern from the expected value pattern storage means 4, and determines whether the two data match. If the comparison means 7 determines that there is no match, the switching control means 8 supplies a new selection signal to the second selection means 6, and
An additional address signal corresponding to the selection signal is supplied to the expected value pattern storage means 4. Thereby, the comparing means 7 compares the output data of other partial logic circuits and the corresponding expected value pattern. If both data do not match, such processing is further repeated. Therefore, depending on the state of the switching control means 8 or the second selection means 6, it is possible to easily know which part of the logic circuit 1 is malfunctioning. Furthermore, since the present invention uses the first selection means 3, input pattern storage means 2, expected value pattern storage means 4, and comparison means 7 common to each partial logic circuit, the circuit configuration becomes simpler than the conventional one. .

【Example】

Hereinafter, one embodiment of the present invention will be described based on the drawings. FIG. 2 shows the configuration of a logic circuit with a self-diagnosis function. The logic circuit 12 includes, for example, partial logic circuits 1 connected in series.
It consists of 2a, 12b and 12c. Normal input data and test input patterns from the input pattern ROM 14 are selectively supplied to the logic circuit 12 via the selector 10. Partial logic circuits 12a, 12b and 12
The output data of c is supplied to the selector 20 to select one of these and supplied to the comparator 18. The comparator 18 uses this data and the expected value pattern ROM 16.
It compares the expected value pattern supplied from A and outputs a mismatch pulse if the two do not match. This mismatch pulse is supplied to flip-flop 22 and held, and also supplied to counter 24 for counting. The counter 24 is a 2-bit counter, and its count value is determined by the upper 2 bits of the address terminal of the expected value pattern ROM 16A, the selection control terminal of the selector 20, and the comparator 18.
is supplied to the control terminal of Expected value pattern ROM16A
The count value of the counter 26 is supplied to the lower address terminals excluding the upper two bits of the input pattern ROM 14 and the address terminals of the input pattern ROM 14. These counters 24 and 2
The count value of 6 is cleared to zero at the rising edge of the TEST signal when the TEST signal is set to high level. This TEST signal and the inverted output value of the flip-flop 22 are connected to the AND gate 28.
When the TEST signal and the inverted output of the flip-flop 22 go high, the AND gate 28 is opened and the clock from the clock generator 30 is supplied to the counter 26 through the AND gate 28 and counted. Next, the operation of this embodiment configured as described above will be explained. When the TEST signal is set to low level, it becomes normal mode.
Normal human data is passed through the selector 10 to the logic circuit 12.
supplied to When the TEST signal is set to high level, it becomes a self-diagnosis mode, and when the TEST signal rises, the flip-flop 22
is reset, its inverted output becomes high level, and the counts of counter 24 and counter 26 are cleared to zero. As a result, the selector 20 selects the partial logic circuit 12.
The output data of c is selected, the upper two bits of the address terminal of the expected value pattern ROM16A become O, and the expected value pattern ROM16A becomes the input pattern ROM.
The expected value pattern of the partial logic circuit 12C for the 14 input patterns is output. Also, the AND gate 28 is opened by the TEST signal, and the clock generator 30
The counter 26 counts the clocks from the input pattern ROM 14 and the expected value pattern ROM 16A, and the read addresses of the input pattern ROM 14 and the expected value pattern ROM 16A are incremented. Then, an input pattern is output from the input pattern ROM 14, and is supplied to the logic circuit 12 via the selector IO. The comparator 18 compares the output data of the partial logic circuit 12c for this input pattern with the expected value pattern from the expected value pattern ROM 16A. If both data match, the output of comparator 18 remains at a low level. If the two data do not match, the comparator 8 outputs a mismatch pulse, the inverted output of the flip-flop 22 becomes low level, and the AND gate 28 is closed. Also, due to this mismatch pulse, the input pattern ROM1
4 becomes 1, the selector 20 selects the output data of the partial logic circuit 12b and supplies it to the comparator 18, and the expected value pattern ROM 16A outputs the expected value pattern of the output of the partial logic circuit 12b to the comparator 18. supply to Comparator 18 compares both of these data. If both data match, the output of the comparator 18 remains at a low level,
The entire circuit is stopped. At this time, the count value l of the counter 24 indicates that the partial logic circuit 12c is in failure. When the output of the partial logic circuit 12b is selected by the selector 20, if a mismatch signal is output from the comparator 18, the count value of the counter 24 becomes 2, and the selector 20 selects the output of the partial logic circuit 12a. Select and comparator 18
The expected value pattern ROM 16A supplies the expected value pattern of the output of the partial logic circuit 12a to the comparator 18. If both data match, the output of the comparator 18 remains at a low level, the entire circuit is stopped, and the counter 2
A count value of 4 indicates that the partial logic circuit 12b is faulty. If the two data do not match, a mismatch pulse is output from the comparator 18 and the count value of the counter 24 becomes 3, the comparison operation of the comparator 18 is stopped, the entire circuit is stopped, and the count value of the counter 24 becomes 3. 3 indicates that the partial logic circuit 12a is defective. If the fault diagnosis operation stops as described above,
By looking at the count value of the counter 24, it is possible to easily know which part of the partial logic circuit 12 is at fault.

【Effect of the invention】

As explained above, the logic circuit with self-diagnosis function according to the present invention uses the first selection means, input pattern storage means, expected value pattern storage means, and comparison means common to each partial logic circuit, so the circuit configuration is is easier than before,
Moreover, it is possible to easily determine which part of the logic circuit is malfunctioning based on the state of the switching control means or the second selection means.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle structure of a logic circuit with a self-diagnosis function according to the present invention. FIG. 2 is a block diagram of a logic circuit with a self-diagnosis function according to an embodiment of the present invention. FIG. 3 is a block diagram showing the principle structure of a conventional logic circuit with a self-diagnosis function. In the figure, 10.20 is a selector 12 is a logic circuit 14 is an input pattern ROM 16 is an expected value pattern ROM 18 is a comparator 22 is a flip-flop 24.26 is a counter 30 is a clock generator device

Claims (1)

[Claims] Logic circuit (1a to 1d) consisting of a plurality of partial logic circuits (1a to 1d)
1); input pattern storage means (2) storing test input patterns to be supplied to the logic circuit; and input pattern storage means (2) for selectively supplying normal input data to the logic circuit and the input pattern to the logic circuit. First selection means (3)
and expected value pattern storage means (4) storing an expected value pattern to be output when the partial logic circuit operates normally in response to the input pattern to the logic circuit; the input pattern storage means and the expected value pattern. Address generation means (5) for supplying an address signal to the value pattern storage means so that the two patterns correspond to each other, and second selection means for selecting one of the outputs of the partial logic circuit in response to the selection signal. (6), a comparison means (7) for determining whether the data selected by the second selection means and the data from the expected value pattern storage means match; In this case, switching control means (8) supplies a new selection signal to the second selection means and supplies an additional address signal according to the selection signal to the expected value pattern storage means; 1. A logic circuit with a self-diagnosis function.