JPH0290077A - Test data generation method - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to fault diagnosis of logic circuits, and particularly to a method for generating test data thereof.

[Conventional technology]

As a method for diagnosing faults in logic circuits, there is a method of detecting faults by giving various diagnosing patterns to the part to be diagnosed and checking whether the output pattern matches a pre-prepared expected pattern. .

2121, a simplified block diagram illustrating the method is shown.

In the figure, ■ indicates an information processing device, 2 indicates a diagnosis control section, and 3 indicates a section to be diagnosed. In the external storage device 10.

Gate input/output connection data and periodic output pattern data are stored in the external storage device 11.0 For diagnosis, gate input/output connection data from the external storage device 10 is stored.
The data is sent to the test data generation section 7 to generate test data. After the test data is stored in the external storage device 9, the first clock signal 12 is applied to the input flip-flop 4 of the logic circuit 5 to be diagnosed, and the test pattern is applied to the logic circuit 8. A signal 13 is applied to send the resulting output data observed in the output flip-flop 6 to the data comparator 8. The data comparator 8 compares the output data with the expected output data 11 to see if they match. By repeating such operations, a failure diagnosis of the part to be diagnosed is performed.

By the way, if you prepare test data in which a large number of output terminals, such as 16 address outputs, change simultaneously from a logic value of 1 to a logic value of O, and input it to an LSI, the current change in the ground line inside the LSI will be detected. is large and generates ground noise, which adversely affects LSI characteristic test 1, for example, input voltage characteristics. Therefore, when generating test data, it is necessary to generate diagnostic data that does not satisfy the condition (prohibition condition) that many outputs change simultaneously.

Here, the "prohibition condition" will be explained using FIG. 3. Figure 3 shows an example of a logic circuit, 14.15,1
6.17 is a NAND gate, A.

B, C, D, and E are input terminals, and F, G, H, and I are output terminals. Also, φ or 1 input to each of input terminals A-H
Let the signals of i□+iat xat 14 and i be, and the signals of φ or 1 output to each of the output terminals F-I be 0□+oz+oa and o4.

Now, the signal j1112+IJ input to input terminal A-E
The set of values of I 14 and i5 is called an input pattern and is expressed as (i 12 + ial 14115).

Similarly, the signal output to output terminal F-I is 0, o2゜0.
, and one set of values of o4 is called an output pattern (o
at 02903904). For example, i□=φ
When r 12 = 1113 = 1114 = φ, i, = 1 (
φ, 1, 1. Since there are five input terminals of the logic circuit in FIG. 3, denoted by φ, 1), the set of input signal patterns is
There are ″′=32 pairs.

Now, if input signal pattern 1 (1, O, 0, 0° 0) and input signal pattern 2 (1, 1, 1,, 1, 1) are continuously input to the LSI, output signal pattern 1 (1, i
, 1.1) and output signal pattern 2 (0, O, 0, 0) are continuously output. At this time, when switching from output pattern 1 to output pattern 2, output terminals F to ■ simultaneously change from logical value 1 to logical value O, and in this case, the number of simultaneous output changes is 4. The number of simultaneous output changes is the set value (for example, 1
An input pattern sequence condition that exceeds 0) is called a "prohibited condition."

Next, test data generation for the circuit shown in FIG. 1 will be explained using a conventional technique.

FIG. 1 shows an example of a logic circuit, where is, 19°20.
21 is a NAND gate, J, L, M.

N is an input terminal, and O, P, Q, and R are output terminals.

Further, it is assumed that the signals of φ or 1 input to each of the input terminals JN are 161 1'l+181 x and lia. Further, the signal of φ or 1 output to each of the output terminals 0-R is assumed to be oit owl Off*O-.

Next, in the circuit shown in FIG. 1, the output φ of the NAND gate 14 is
Generation of test data for detecting stuck-at faults will be explained. Here, the φ stuck-at fault refers to a failure in which the logical value is fixed to φ.

The input signal pattern A (1, φ, φ, φ
, φ) of the output of the zero-order NAND gate 14
The 0th-order N
The input signal pattern C (1, O, O, i.

1) Generate. For input signal patterns A-C, output signal pattern A (1, 1, l, l), output signal pattern B (0, O, 0, 0), output signal pattern C (1
, l, O, O) correspond. Input signal patterns A-C and output signal patterns A-C are sequentially stored in memory.

An example of a related test data generation method of this type is JP-A-57-175263.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, input signal patterns are input to the LSI in the order in which they are stored in the memory. Therefore.

If the maximum value of the number of simultaneous changes is 4, there is a problem that if input to the LSI in the order stored in the memory, the prohibition condition will be satisfied and the data will not be suitable as test data. Thus, even if the generated test data satisfies the prohibition conditions, it is an object of the present invention to provide a method for generating valid test data by avoiding the prohibition conditions as much as possible.

[Means to solve the problem]

The above purpose is to check whether there is any data that satisfies the prohibition conditions in the test data stored in memory, and if
If the prohibition condition is satisfied, the test sequence is rearranged to avoid the prohibition condition.

Here, the recombination of test sequences means, for example, changing the sequences of input signal patterns A, B, and C into one.

This refers to changing the sequence of input signal patterns A, C, and B.

[Effect]

The recombination of test sequences will be explained below. Now, input signal pattern A is used as test data for the logic circuit.
, B, and C are prepared. Output signal pattern A for input signal patterns A, B, and C
, B, and C correspond.

The output signal pattern Δ is (1, 1, 1, 1), the output signal pattern B is (0, O, 0, 0), and the output signal pattern C is (1, 1,, O, O). Here, if the test sequences are A, B, and C, the number of simultaneous output changes is four.

Test sequences A and C.

If B, the number of simultaneous output changes is 2. Recombining the test sequence means changing the input signal pattern sequences prepared in advance to A and B based on the information on the number of simultaneous output changes.
, C to A, C, B. This reduces the number of simultaneous output changes from 4 to 2, making it possible to prevent ground noise from occurring.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the flowchart of FIG. 1, and a procedure for generating test data for the circuit shown in FIG. 4.

First, it is assumed that the output of the NAND gate 18 has a φ stuck-at fault (102), and then the input signal pattern is as follows.

The 5-person chi δ pattern A (1, 0,
0,0,0) is obtained (104) and stored in memory (
105), similarly, 1 of the output of the NAND gate 18
Assuming a stuck-at fault (102), input signal pattern B (
1, l, 1, 1.1) (104) and store it in the memory (105).Similarly, assuming a stuck-at-1 fault at the output of the NAND gate 20, the input signal pattern C
(1°0.0, 1.1) is obtained (1,04) and stored in memory (105).

Next, the input signal pattern stored in memory.

If input to the LSI in the stored order (test order 1 in Figure 4), the number of simultaneous output changes will be 4 (106), satisfying the prohibition condition (in this case, set to 4), and input it as test data. Not suitable (107).

Therefore, when input signal pattern B and input signal pattern C are exchanged (test order 2 in FIG. 4) (108) and input to the LSI, the number of simultaneous output changes becomes two.

Does not satisfy the prohibition conditions and is valid as test data (
109).

Although the above-described embodiment was applied to a logic circuit consisting of four NΔAND gates, it goes without saying that it can also be applied to a large-scale logic circuit having more than 100 output terminals.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to avoid generation of test data that adversely affects conventional LSI characteristic tests. As a result, the accuracy of the LSI characteristic test is improved and the LSI can be evaluated correctly.

[Brief explanation of drawings]

Fig. 1 is a flowchart of test data generation according to an embodiment of the present invention, Fig. 2 is an explanatory diagram showing an example of a conventional diagnosis method, Fig. 3 is an explanatory diagram showing an example of prohibition conditions, and Fig. 4 is a test data generation flowchart. It is an explanatory diagram showing an example of data. 1... Information processing device, 2... Diagnosis control unit, :3-.
・Diagnosed unit, 7: Test data generation unit, 8: Data comparator g: Test data storage unit, 10: Goo 1-human output connection data storage unit, 11: Expected output data Storage section, 12-13...clock signal. Nominal illustrated collection

Claims (1)

[Claims] 1. Apply multiple input patterns for diagnosis to the part to be diagnosed, and compare the output pattern actually obtained from the part to be diagnosed with the expected value pattern set in advance, and evaluate the part to be diagnosed over multiple tests. In a diagnostic method that performs diagnosis, when generating a pattern to detect a certain fault in the part to be diagnosed, a large number of output terminals are changed simultaneously to automatically avoid generating patterns that adversely affect the characteristics of the logic circuit. A test data generation method characterized by: