JPH03180932A - Instruction decoder - Google Patents

Abstract

PURPOSE:To easily decode codes by converting an ID part into a sequential number at the time of receiving an instruction and then applying the converted sequential number to respective control signal parts (blocks). CONSTITUTION:At the time of receiving an instruction code, a code conversion part 31 converts the ID part of variable length bits into a continuous sequential number. Thereby, the format of the converted instruction is constituted of the sequential number, an instruction set and a machine code. In each block 30, a code decoding part 30a receiving the output of the code conversion part 31 decodes the sequential number again and a control signal forming unit 30b generates a control signal. Since respective sequential numbers are simply allocated to respective instruction in a certain order, the code decoding of respective blocks 30 can easily be executed.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide an instruction decoding device that generates a control signal by decoding an input instruction code and has less signal delay without increasing the circuit scale. In the instruction decoding method of the distributed control method, the control signal generation section is divided into multiple blocks, and each block is provided with a code decoding section for decoding instructions and a control signal generation unit for generating control signals. A code conversion unit is provided that converts the ID part of the instruction code to be processed into a continuous sequential number, and each block is given the output of this code conversion unit, and each block receives the output of the code conversion unit and decodes the sequential number again. and configured to generate a control signal.

[Industrial Application Field] The present invention relates to an instruction decoding device that decodes an input instruction code and generates a control signal.

The RI5C (Reduplicator) uses a small digital signal processor (DSP) and instruction set to execute instructions at high speed.
ced In5tructionSet Com
(puter), instructions must be decoded at extremely high speed.

Furthermore, in order to operate at high speed, the bit width of the instructions of these devices is set to be large (for example, 32 bits). Therefore, instruction decoding is performed using PLA (Pr.

It could not be constructed using only devices such as gramable logic arrays, and had to be constructed using random gates. For this reason, the complexity and circuit scale during circuit design have increased, and the number of design steps has increased. Therefore, it is required that the circuit scale of the instruction decoding device be reduced.

[Prior Art] FIG. 7 is a block diagram showing an example of the configuration of a DSP. DS
P is broadly divided into program sequence control blocks 1. Address calculation block 2. Operation block 3. It consists of a special register/counter block 4 and an I10 interface block 5. Among these, the part that decodes instructions is the program sequence control block.

In the program sequence control block], 1a is a ROM in which a program to be executed is stored.

]b is the lROM1. An instruction register (IR) that reads and holds the contents of a; lc is a decoder that extracts and decodes the contents of R1b; and d is lROM1a.
This is a program counter (PC) that gives an address to the program counter.

Here, the instructions stored in the 1ROM 1a have a format as shown in FIG.

(a) shows the case with operand specification, and (b) shows the case without operand specification.

The ID shown in the figure indicates an identification bit for distinguishing between instructions. Generally, some instructions have operands and some do not.

For those with many operands, use I with a short number of bits.
D and many bits of I for instructions with no operands.
By allocating D, the bit length of the entire instruction can be shortened. Therefore, RIS requires that one instruction be expressed in one word.
The above-mentioned technique is often used in C processors.

FIG. 9 is a block diagram of a conventional instruction decoding system. 8th
An instruction having a format as shown in the figure is decomposed by the decoder 10 into signal lines corresponding to the instruction. As for the output of the decoder 10, one signal line corresponds to one instruction. Therefore,
As many signal lines as there are instructions are required. The decomposed signal is a control signal! The signal then enters the bottom section 11 and is reorganized into each control signal. In this method, all control signals required for each block are created at once.

FIG. 10 is a block diagram of another conventional instruction decoding method. The example shown in the figure is divided into functional blocks such as a timer block, an addition block, and a multiplication block. The commands arriving on the command bus 2o enter each block 21. In each block, the decoder 21a decodes the command, and the generator 21b generates a control signal according to the decoding result. This method is a distributed method that generates a necessary control signal for each block.

[Problem to be solved by the invention] Although the method shown in FIG. 9 can reduce the circuit scale, it is difficult to design because a large number of control signals are generated at once. Furthermore, the wiring length of the control signal increases, and the signal delay increases. Furthermore, the number of wires between blocks increases,
There is a problem that chip layout becomes difficult. On the other hand, in the method shown in FIG. 10, a control signal is generated for each block, so there is little delay in the control signal, and wiring on the chip is easy. On the other hand, since the same decoding section is provided between each block, the circuit scale becomes large.

Furthermore, since the instruction bus is wired to each part of the chip, there is a problem that layout is difficult.

The present invention has been made in view of these problems, and an object of the present invention is to provide an instruction decoding device with less signal delay without increasing the circuit scale.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
Reference numeral 30 denotes a plurality of blocks, which are obtained by dividing the control signal generation section into a plurality of blocks. Each block 3o is provided with a code decoder 30a that decodes instructions and a control signal generation unit 30b that generates control signals. 31 is a code conversion unit that converts the ID part of an input instruction code into a continuous sequential number; 32 is each block 3;
0 and the code converter 31.

[Operation] When the code converter 31 receives an instruction code, it converts the variable length bit ID part into a continuous sequential number.

The converted instruction format consists of a sequential number, an instruction set, and a machine code, as shown in FIG.

In each block 30, upon receiving the output of the code conversion section 31, the code decoding section 30a decodes the sequential number again, and the control signal generation unit 30b generates a control signal.

Here, the sequential number is a simple number assigned to each instruction in a certain order, and the code of each block 30 can be easily decoded. Moreover, by adopting such a configuration, there is no need to increase the circuit scale, which is a drawback of the distributed control method (see FIG. 10), and it can be realized using fewer buses than the instruction bus. Also, FIG.

In the conventional example shown in Fig. 10, it was difficult to create test data when simulating each block, but according to the present invention, the input data for control can be simply counter output, and the test data can be generated automatically. This makes it possible to perform simulations easily.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the instruction decoding section. Components that are the same as those in FIG. 1 are designated by the same reference numerals. The illustrated embodiment shows the code decoder 30a and control signal generation unit 30b of FIG. The sequential numbers coming in via the instruction bus 32 are processed by a binary decoder 40.
decoded by FIG. 4 shows the logic of the decoder when there are three inputs.

The output of the binary decoder 40, which is decoded as shown in FIG. 4 according to the input, enters a multi-input OR gate 41. The output of the OR gate 41 enters a flip-flop 42, is latched by a clock, and is output as a control signal.

FIG. 5 is an explanatory diagram of the operation of the code converter 31.

It is assumed that a machine code as shown in (a) is input. As shown in FIG. 8, this machine code has different lengths of ID bits depending on the type of instruction. ID
It is assumed that the width varies from 1 bit to a maximum of 5 bits. When such a machine code is input, the code converter 31 converts the code into a 4-bit code using the logic shown in (b). Regardless of the size of the ID bit width, all IDs are converted into 4-bit sequential numbers.

The 4-bit sequential number converted in this way then enters the code decoder 30a.

FIG. 6 is a timing chart showing the operation of the present invention. (a) shows the operation of the program counter, (b) shows the operation of the instruction register IR, (C) shows the operation of the instruction register IRI, and (d) shows the operation of the instruction register IR2. Instruction execution is performed in a pipeline. The instruction at address n indicated by the program counter is read into the instruction register IR. Then, code conversion is performed over one machine cycle during the period (■) in the figure.

The code-converted instruction is instruction register I.
RI is entered, and the code is decoded during the period marked ■ in the figure.

The decoded data is stored in instruction register IR2.
The control signal is output during the period indicated by ■ in the figure.

[Effects of the Invention] As described above in detail, according to the present invention, the ID part is converted into a sequential number in response to a command, and then given to each control signal generation unit (block), thereby each block Then, all you have to do is decode the sequential numbers, which makes the code easier to decipher. Therefore, according to the present invention, there is no need to increase the circuit scale. Furthermore, since a distributed method is adopted, an instruction decoding device with less signal delay can be provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a diagram showing the instruction format after conversion, Fig. 3 is a block diagram showing an embodiment of the instruction decoding section, and Fig. 4 is a diagram showing the logic of the decoder. , FIG. 5 is a diagram illustrating the operation of the code converter, FIG. 6 is a timing chart showing the operation of the present invention, FIG. 7 is a block diagram showing an example of the configuration of a DSP, and FIG. 8 is a diagram showing the instruction format. FIG. 9 is a block diagram of a conventional instruction decoding method, and FIG. 10 is a block diagram of another conventional instruction decoding method. In FIG. 1, 30 is a block, 30a is a code decoder, 30b is a control signal generator, 31 is a code converter, and 32 is an instruction bus. the law of nature

Claims (1)

[Claims] The control signal generation unit is divided into a plurality of blocks (30), and each block (30) includes a code decoding unit (30a) that decodes instructions and a control signal generation unit that generates control signals. (30b) is provided with a code converter (31) that converts the ID part of an input instruction code into a continuous sequential number, and each block (30) is equipped with a code converter (31) that converts the ID part of an input instruction code into a continuous sequential number. The instruction decoding device is configured to receive the output of the code conversion unit (31), and each block receives the output of the code conversion unit (31), decodes the sequential number again, and generates a control signal.