JPH03181090A - Refresh method for dynamic ram - Google Patents

Abstract

PURPOSE:To reduce the number of circuits for refresh by inputting the overflow signal, which a free-running timer periodically generates, as an interrupt signal and refreshing a dynamic RAM by the interrupt handling based on the interrupt signal. CONSTITUTION:The overflow signal which a free-running timer 15 provided in a microcomputer periodically generates is outputted to a central processing unit 11 as the interrupt signal. The central processing unit 11 refreshes a dynamic RAM 14 by an interrupt routine based on the interrupt signal. The dynamic RAM 14 is refreshes by the interrupt routine of the central processing unit 11 at each time of overflow of the free-running timer 15 in this manner. Consequently, a dynamic RAM controller for refresh is unnecessary, and the central processing unit 11 accesses the dynamic RAM 14 like a static RAM. Thus, the number of circuits for refresh is reduced.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a refresh method for a dynamic RAM, and more specifically, a refresh method for a dynamic RAM provided in a microcomputer, which can be accessed by a central processing unit like a static RAM, and which can be used for refreshing. Dynamic RAM that can reduce the number of circuits
A dynamic RAM refresh method, in which a central processing unit inputs an overflow signal periodically generated by a free running timer as an interrupt signal, and executes an interrupt routine based on this interrupt signal. The dynamic RAM is refreshed by the following.

[Industrial Field of Application] The present invention relates to a method for refreshing a dynamic RAM, and more particularly to a method for refreshing a microcomputer equipped with a dynamic RAM.

Since dynamic RAM can be more highly integrated than static RAM, the R
In order to increase the integration density of AM, dynamic RAM is increasingly being adopted in place of static RAM. When adopting a dynamic RAM, there is a refresh function that is not available in a static RAM, and therefore, a periodic refresh processing operation is required.

[Prior Art] In recent years, dynamic RAM (hereinafter referred to as DRA~1) CI has become more popular than static RAM (hereinafter referred to as SRAM).
) DRAM has been adopted in microcomputers because it is superior in terms of integration. As shown in FIG. 2, the central processing unit (hereinafter referred to as CPU) l has address and data buses 2 and 3.
Data is exchanged with the DRAM 5 via the arbiter circuit 4. The arbiter circuit 4 refreshes the DRAM 5 based on a refresh signal periodically output from the refresh counter 6.

Further, the arbiter circuit 4 prohibits access from the CPUI during the refresh period, that is, does not output an access permission signal to the CPU 1.

[Problems to be Solved by the Invention] Therefore, the DRAM 5 is inferior to the SRAM in that the CPU cannot access the DRAM 5 during the refresh period.

Further, the DRAM 5 has an arbiter circuit 4 for refreshing. Since it is necessary to provide a DRAM controller such as a refresh counter 6, there is a problem in that the number of circuits increases.

The present invention has been made to solve the above problems, and its purpose is to refresh dynamic RAM, which can be accessed by a central processing unit like static RAM, and which can reduce the number of refresh circuits. The goal is to provide a solution.

[Means for Solving the Problems] In order to achieve the above object, the present invention causes a free running timer provided in a microcomputer to output an overflow signal periodically generated as an interrupt signal to a central processing unit.

The central processing unit refreshes the dynamic RAM through interrupt processing based on this interrupt signal.

[Operation] The dynamic RAM is refreshed according to the interrupt routine of the central processing unit every time the free running timer overflows by Q times.

Therefore, a dynamic RAM controller for refresh is not required. Moreover, the central processing unit can access the dynamic RAM like a static RAM.

[Example] An example embodying the present invention will be described below with reference to the drawings.

FIG. 1 is a system diagram of a microcomputer for implementing the present invention.

In Figure 1, the central processing unit (hereinafter referred to as CPU)
11 is a dynamic RAM (hereinafter referred to as DRAM) 1 via an address bus 12 and a data bus 13.
4 is connected. The free running timer 15 counts the count clock signal from the oscillation circuit 16,
When it reaches a predetermined value, that is, when it overflows, it is reset and starts counting again from the beginning, and the operation is repeated. The free running timer 15 outputs the current count value to the CPU II, and also outputs an overflow interrupt signal to the interrupt control circuit 17 when it overflows. Therefore, free running timer 1
5 outputs an overflow interrupt signal to the interrupt control circuit 17 every time there is an overflow (every fixed period).

The interrupt control circuit 17 notifies the CPU II of the interrupt caused by the free running timer 15 based on the overflow interrupt signal, and also outputs a refresh signal for prohibiting data output to the DRAM I. In addition, the interrupt control circuit 17 is configured to input several other interrupt signals, and when one interrupt signal is input, other interrupt signals are not input until the CPU II interrupt routine due to that interrupt is completed. They are supposed to wear masks.

Next, the operation for refreshing the DRAM 14 of the microcomputer configured as described above will be explained.

Now, while the CPU II is operating according to the main routine, if the free running timer 15 overflows, the timer 15 sends an interrupt to the interrupt control circuit 17.
Outputs an overflow interrupt signal. The interrupt control circuit 17 provides a free running timer 15 to the CPU 11.
outputs an interrupt signal based on overflow that occurs periodically. Based on this interrupt signal, CPU II
DRAM14 from the main routine that has been performed so far.
Enters an interrupt routine to refresh the . C
In this interrupt routine, the PU 11 performs a processing operation to refresh the DRAM 14 via the address and data bus 12.13 based on a refresh program prepared in advance. During this refresh, the main routine is temporarily halted (HALT), so DRAM 14 is not accessed.

Then, when the refresh process is finished, CPU1l
returns to the main routine and re-executes the user program. Thereafter, every time the free running timer I5 overflows, that is, periodically, the DRAM14 is
It is refreshed in II. Note that the free-running timer is used for clock counting when displaying the time, for canceling power-on reset, as a watchdog timer, and so on, so it can also be used for the same purpose.

In this way, in this embodiment, the CPU II performs interrupt processing based on the overflow interrupt signal periodically generated by the free running timer 15, and the DRAM 1 4 is refreshed by the interrupt processing. A refresh counter and an arbiter circuit for refresh can be eliminated, the system configuration of the microcomputer can be simplified accordingly, and there is no need to consider refresh.

[Effects of the Invention j As detailed above, according to the present invention, static RA
It can be accessed by the central processing unit like M, and has the effect of reducing the number of refresh circuits.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing a microcomputer for implementing the present invention, and FIG. 2 is a system diagram showing a conventional microcomputer. In the figure, ti is the CPU. 14 is a dynamic RAM, and 15 is a free running timer.

Claims (1)

[Claims] A dynamic RAM refresh method, wherein a central processing unit inputs an overflow signal periodically generated by a free running timer as an interrupt signal, and refreshes the dynamic RAM by an interrupt routine based on this interrupt signal. A dynamic RAM refresh method characterized by performing the following steps.