JPH03181091A - Memory device provided with dram - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device equipped with a DRAM, and more particularly to means for refreshing the DRAM of a memory device.

[Conventional technology]

There are microcontroller boards for microcomputers that are composed of a CPU, ROM, RAM, etc., controller boards for various devices, and the like.

RAM as its component or removable R
AM element, RAM module (board consisting only of RAM elements), RAM board (in addition to RAM, some ROSIC I
In general, one element has a large capacity and is inexpensive, so RAM
is often used.

However, in DRAM, data is stored depending on the presence or absence of electric charge accumulated in each unit memory in an extremely small capacity, so in order to continue to memorize the stored data, it is necessary to store all the data within a certain period of time, for example, Bms. It is necessary to refresh (update) the contents of the unit memory as is, and the same current is consumed as in normal write and read accesses each time.

In this way, DRAM requires refreshing,
The disadvantage is that it cannot normally be accessed during refresh.

For example, if we consider a controller (board) for a printer, as its performance increases, such as faster speeds, higher resolution, larger paper sizes that can be processed, and 2-sided printing, the required memory capacity (same as the installed capacity) increases. is increasing dramatically.

If a large-capacity DRAM is refreshed all at once, an excessive current exceeding the maximum permissible current of the power supply will flow at that moment, causing problems such as voltage drop, so the entire DRAM is divided into multiple areas. A method has been adopted in which each area is refreshed (at different times).

However, for example, in the case of a controller for a printer, whether it is a high-performance printer or a low-performance printer, it is basically the same; the only difference is the data processing speed and memory capacity. .

Therefore, it is important to standardize the standards as much as possible, use controllers with high data processing speeds for printer engines with slow processing speeds, and add memory to printer engines that require large memory capacities. This is desirable in terms of production management and cost measures.

[Problem to be solved by the invention]

However, in general, the controller itself does not have a power source, and is often supplied with power from a device that is combined with the controller.

High-performance devices with large memory requirements can afford to supply large currents, while devices with small memory requirements generally do not have the same margin.

Therefore, if you subdivide the memory and increase the number of areas to suit a device with limited capacity, the number of refreshes will increase and the total time required for refresh will increase accordingly, which will shorten the time that can normally be accessed and reduce the use of memory. Efficiency or performance decreases.

Furthermore, if the area is reduced according to a device with sufficient margin, performance will improve, but there is a problem in that an excessive current exceeding the maximum permissible current of the power supply will flow, increasing the risk of causing a serious accident.

This invention was made in view of the above points, and DR
A DRA that performs refresh with good performance without the risk of a refresh current exceeding the power supply capacity flowing, corresponding to the installed capacity of the AM or the power supply capacity supplied.
An object of the present invention is to provide a memory device with M.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a memory device equipped with a DRAM whose mounting capacity can be changed by attaching and detaching a part of the DRAM, including mounting capacity detection means for detecting the mounting capacity of the DRAM; A region setting means for dividing the DRAM into one or more regions according to the mounting capacity detected by the mounted capacity detection means, and a refreshing means for refreshing the DRAM for each region divided by the region setting means. It was established.

Alternatively, a DRA can selectively connect devices with different power capacities that can be supplied to this memory device.
A memory device equipped with M includes a power capacity detection means for detecting the power capacity that can be supplied to this memory device from a connected device, and one or more DRAMs according to the power capacity detected by the power capacity detection means. The DRAM is provided with an area setting means for dividing the DRAM into separate areas, and a refresh means for refreshing the DRAM for each area divided by the area setting means.

In addition, in a memory device equipped with a DRAM, devices having different power supply capacities that can be supplied to the memory device can be selectively connected, and the mounting capacity can be changed by attaching and detaching a part of the DRAM. a power supply capacity detection means for detecting the power supply capacity that can be supplied to this memory device from a device installed in the memory device; a mounting capacity detection means for detecting the mounting capacity of the DRAM; The area setting means divides the DRAM into one or more areas according to the detected power supply capacity, and the refresh means refreshes the DRAM for each area divided by the area setting means. .

Furthermore, a power supply information setting means is provided for setting information on the power supply that can be supplied to the memory device from a connected device, and a power supply capacity detection means detects the power supply capacity based on the power supply information set in the power supply information setting means. You may also do so.

Alternatively, an information input means for inputting information from a connected device is provided, and a power supply capacity detection means detects the power capacity it that can be supplied from the connected device to this memory device based on the information input by the information input means. You may also do so.

[For production]

With the above configuration, when the power supply capacity is known in advance, the mounted capacity detection means detects the mounted capacity of the DRAM, and the area setting means sets the mounted capacity of the area according to the power supply capacity. The optimum number of areas is set by dividing by the size, and the DRAM is refreshed for each set area.

Next, if the mounting capacity is known in advance.

The power capacity detection means detects the power capacity that can be supplied to this memory device from the connected device, and the area setting means sets the optimum number of areas by dividing the installed capacity by the size of the area according to the power capacity. , DRAM for each set area
refresh.

Furthermore, if neither the power supply capacity nor the mounted capacity is known in advance, the power supply capacity detection means and the mounted capacity detection means detect the power supply capacity and the mounted capacity, respectively, and the area setting means sets the mounted capacity to the power supply capacity. Set the optimal number of areas by dividing by the size of the corresponding area, and then
refresh.

Therefore, there is no fear that a refresh current exceeding the power supply capacity will flow, and refresh with good performance can be performed.

Further, the power capacity detection means detects the power capacity by setting the power capacity of the device connected to the power capacity setting means or by inputting necessary information from the device connected to the information input means. I can do it.

〔Example〕

Embodiments of the printer according to the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of a printer controller (hereinafter simply referred to as "controller"), which is the main part of the printer's control system.

The controller 1 includes a CPU (central processing unit) 10 and a C
Program ROM II stores programs and constant data for PUl0 to control controller 1 according to the program, font ROM 12 stores fonts for converting single character codes into character data expanded into bitmaps, and variable data such as character codes and counters. RA that stores
M13, a VRAM (also referred to as r-bitmap memory) 14 that stores data developed and edited into bitmaps before outputting characters, figures, etc. to the printer engine 2 as image data, and a CPU 10 that stores data that has been expanded and edited into a bitmap before outputting characters, figures, etc. to the printer engine 2 as image data. Host machine 3. Interface (I/F) for inputting and outputting commands and data to and from the operation panel 4
Engine I/F 15, host I/F 16. It consists of a panel I/F 17 and a removable additional RAM 18, which are connected to each other by a pass line.

Here, the RAM 15, VRAM 14, and additional RAM 18 are all composed of DRAM and are classified according to their functions, but the fixed RAM installed on the board of the controller 1
Total RAM mounting capacity (also referred to as "memory capacity"), including M and additional RAM18 added later as necessary
are used by assigning addresses according to the capacity required for each.

The controller 1 controls the entire printer according to the mode specified by the operator and the mode instructed by the host machine 3. The controller 1 also controls the printer engine 2 after inputting original data from the host machine 3 and editing it into image data. It has a function of displaying a specified mode, printer status, progress status, error messages, etc. input from the printer engine 2 on the operation panel 4.

The CPUIQ operates according to the program stored in the program ROM 11 according to the mode instructed by the host machine 3 via the host I/F 16 and the mode specified by the operator via the operation panel 4 via the panel I/F 17. Controls the controller 1 and the entire printer.

In addition, the CPUIQ instructs the printer engine 2 (engine driver, not shown), inputs and processes the progress status of printer status 1 work, presence or absence of errors, etc., and sends necessary information via the panel I/F 17. Operation panel 4
displayed on a display section (not shown).

Furthermore, the CPUIQ inputs manuscript data consisting of character codes, graphic data, etc. from the host machine 3 via the host I/F 15, and converts the character codes into character data developed into a bitmap using the font stored in the font ROM 12. The converted graphic data with gradation is developed into a bitmap by dither processing, etc., and edited into one page (two pages in the case of double-sided printing) of image data along with the binary graphic data that has already been input as a bitmap, and stored in VRAM1.
4, and outputs it to the printer engine 2 as a video signal synchronized with a clock signal outputted from the printer engine 2 at timing, and prints it.

Power for operating the controller 1 is supplied from a printer engine 2, which is a device that generally supplies power, although not shown, and most of the power is used to refresh the DRAM.

The memory capacity of the DRAM to be mounted largely depends on the performance of the printer, that is, the performance of the printer engine 2, and the higher the performance, the greater the mounting capacity.

For example, if a dot printer has a slow processing speed, it can be processed by preparing VRAM for several lines, but a laser printer, which has a fast processing speed, may print the same page repeatedly, so it can process at least one page. If a VRAM is required and a one-sided printing function is provided, it is necessary to prepare a VRAM for at least two pages.

Also, as the maximum paper size that can be printed increases, considering the 35th edition as a standard, if the maximum paper size is A4, it will be 1.33 times, if it is 84, it will be twice, if A3, it will be 2.67 times, and if it is 33, it will be 1.33 times. Each requires four times the capacity of VRAM.

Furthermore, as the resolution increases, the capacity of VRAM increases in proportion to the square of the resolution, so at a resolution of 150 dpi (
200 dpi (dots per inch)
1.78x at 240dpi, 2.56x at 240dpi, 300x
dpi requires four times the capacity, and 400 dpi requires 7.11 times the capacity of VRAM.

Each of these elements is not independent, but performance is improved by balancing each other, so as performance improves, the mounting capacity of DRAM increases dramatically, and the required power (current) also increases almost proportionally. increases.

Therefore, the controller 1 is equipped with an additional RAM 18 having a capacity sufficient to match the performance of the printer engine 2 to which it is combined, and the printer engine 2's power supply supplies power to the controller 1 in addition to the power it itself requires. Usually, printer engines are set to supply power according to their installed capacity, but not all printer engines can supply well-balanced power.

FIG. 1 is a block diagram showing the configuration of a first embodiment of a memory device of a controller 1 according to the present invention.

As shown in the figure, a CPU 10, a DRAM device 20, and a refresh device 30 that constitute a memory device equipped with a DRAM are connected to an engine I/F 413 of a printer engine 2 via a controller I/F 47 thereof.
/F 15 and other I/Fs (not shown), ROM, etc., and the data bus 41, address bus 42. They are connected by a path line 40 consisting of a control bus 43.

The DRAM device 20 includes a DRAM 21 and a memory controller 22.
and an address generation section 23.

As already explained, DRAM21 is RAM13, V
RAM14. All installed RAMs including the additional RAM 1B (FIG. 4) are shown, and write/read data is input/output via a connected data bus 41.

In this embodiment, the maximum mounting capacity of the DRAM 21 is made up of 16 blocks, blocks 0 to 15, with eight 256K x 4-bit IM bit I) RAM elements, ie, 256K x 32 bits, as two blocks.

The memory control section 22 and the address generation section 23 are connected to each other and jointly control the DRAM 21 not only during normal access but also during refreshing.

The memo 94118 section 22 has an address bus 42. A control bus 43 is connected, and during normal access, a negative logic row address strobe signal (row address strobe signal:
/RAS of negative logic, a column address strobe signal (column address strobe signal; hereinafter referred to as "/CAS"), and a write enable signal or successive enable signal (hereinafter referred to as "/CAS"), respectively. r/WE, 10E") is output from the DRAM 214m.

At the time of refresh, a negative logic refresh /RAS is input from the refresh/RAS generation unit 34 (described later) of the refresh device 50 and output to the DRAM 21, but at this time, /WE and 10E are both in the "H-" refresh mode, and / CAS becomes irrelevant.

The address generating section 23 specifies an address by dividing the full address input from the address bus 42 into a row address and a column address and outputting them to the DRAM 21 during normal access.

During refresh, only the row address input from a refresh address counter 33 (to be described later) of the refresh device 30 is output to the DRAM 21.

The refresh device 30 includes a refresh division number control section 31 and a refresh control section 32, which are area setting means,
It is composed of a refresh address counter 33 and a refresh/RAS generating section 34, which are refresh means.

The refresh division number control unit 31 includes a data bus 41, an address bus 42 . Control bus 43 is connected and D
Data regarding the installed capacity of the RAM 2 l or the power supply capacity supplied from the printer engine 2 is input, and the number of divisions into areas for refreshing the DRAM most effectively is determined and outputted to the refresh control unit 32 .

The refresh control unit 32 divides the mounted DRAM block into one or more areas according to the input division number, and sets timings for the refresh address counter 33 and the refresh/RAS generation unit 34 respectively at the time of refresh. output the necessary data or signal.

The refresh address counter 53 is a 2g up counter that repeatedly counts, for example, from 0 to 511 at a predetermined period synchronized with the refresh cycle, and its contents are updated by a command from the refresh control unit '52 at the time of refresh. It is output to the DRAM 21 as a row address via the address generation section 23.

The refresh/RAS generating unit 34 cyclically updates each divided area to be refreshed at a time according to data input from the refresh control unit 32, and generates one or more blocks belonging to each divided area. The number is output to the memory control unit 22 as /RAS.

For example, if the implementation capacity is 4 blocks consisting of blocks O to 3, the number of divisions is "2", that is, the area is composed of 2 blocks, and blocks 0 and 1 and blocks 2 and 3 are refreshed alternately, / RASO.

1 and /RAS2.3 are alternately output to the memory control unit 22 during refresh, and the memory control unit 22 outputs /WE, 1
Set 0E to °H° and input/RAS and DRA
The specified block is refreshed by outputting it to M21.

During normal access, a 256K (x4 bits) DRAM receives 0 to 511 row addresses (row addresses) and column addresses (column addresses) each consisting of 9 bits.
An address is specified as the intersection, but only the row address is input during refresh, and when the strobe signal is applied, 512 addresses with the same row address are identified as 1.
refreshed from time to time.

Therefore, to refresh an area, let B be the number of blocks that make up the area.

BX512X32 bits will be refreshed per 10-access, which will be repeated 512 times.

Generally, the maximum permissible refresh cycle for a 1M bit DRAM is 81u, so 5120-accesses must be made within that time, and the l-row access cycle T is 8L11
It is within 512=15.625 μs.

FIG. 2 is a timing diagram showing an example of a refresh cycle performed during a period T of 10-access. Figure CB) shows the number of divisions D=
An example of the case of 16 is shown in the same figure (C).

(D), (E), and (F) are D=8 and D, respectively.
Two examples in the case of =4 are shown below.

In FIGS. 2(B) to 2(F), the numbers shown below the waveforms during refresh are provisionally added to indicate the different areas, and do not indicate block numbers or /RAS numbers.

For example, when D=4, one area has 1 to 4 D
=8, each block is composed of one or two blocks.

If the number of regions, that is, the number of divisions is D, this is repeated 0 times, so if D is the maximum value of 16, the refresh interval is 15.625 μs/l 6
40.98 μs, and if the time required for a refresh cycle is 0.45 μs, then 0.45 μs× 16 = 7.2 μs of the row access cycle T = 15.625 μs is used for refresh, Normally accessible time is 8.425
With only μS, the memory usage efficiency, that is, the performance, drops to 54% as shown in FIG. 2(B).

If the number of divisions D = 8 or 4, respectively, Fig. 2 (C)
, (D) or (E), as shown in (F-).

Since the refresh time is reduced to 3.6 μs or 1.8 μS and the performance is improved by 77% or 88%, it is clear how important the optimal decision on the number of divisions is.

As already explained, one block consists of 256 x 32 bits, or 1 Mbyte, and an instantaneous current of about 0.5 A is required to refresh one block.

From the above explanation, an example of the optimal number of divisions derived from the mounting capacity (M bytes) of the DRAM and the power supply capacity is shown in the table.

Next, the operation of the CPU 10, which is the mounted capacitance detection means, will be explained.

When the power is turned on, in many cases, the installed capacity and power capacity are not known, so to prevent excessive current from flowing, the CPU1
O is the maximum number of divisions 116 in the refresh division number control unit 31.
” and start refreshing.

Next, the CPU 10 is set in advance to "0" and "1".
The installed capacity can be detected by writing specific data containing a mixture of data into each block, sequentially reading it out, and comparing it with the written data.

In other words, the blocks whose read data matches the written data are implemented, and the blocks that do not match are not implemented, so which of blocks 0 to 15 is implemented and the total installed capacity? It is detected how many blocks or how many Mbytes there are.

If the power supply capacity is determined in advance and a table of the number of divisions for the mounted capacity is stored in the ROM, when the mounted capacity is detected, the data or the number of divisions is output to the refresh division number control section 31. The area is set by
Optimal refreshment is performed.

The operation of CPUIQ, which is a power supply capacity detection means, will be described below when the @source capacity is not known in advance.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the memory device, which is the same as the first embodiment except that a power information setting device 50, which is a power information setting means, is provided. Explanation of parts with the same reference numerals will be omitted.

The power information setting device 50 includes a data bus 41. Address bus 42. A path line 40 consisting of a control bus 43
are connected to each other and to other devices via a path line 40.

This power information setting device 50 selectively
When connecting the printer engine 2, which is a device that is connected to the
This is for manually setting information such as power supply capacity data, a code corresponding to the power supply capacity, the ID number or machine number code of the printer engine 2, etc.

Or engine I/F15 and controller I/F4
The information on the printer engine 2 may be mechanically detected and set by determining the shape of a connector connecting the printer engine 7 or a power connector (not shown).

When the power is turned on, as already explained, the CPU 10 first sets the maximum division number "16" and starts refreshing, and then detects the installed capacity of the DRAM 21.

Next, the CPU 10 reads the information of the printer engine 2 set in the power supply information setting bag W50, and if the information directly indicates the power capacity, it is stored as is, or if it is other information, it is stored in the ROM in advance, for example. The power supply capacity can be detected using the comparison table provided.

Either the power supply capacity detection or the mounting capacity detection may be performed first, but if both are detected, the optimum number of divisions can be obtained from the table already shown.

In the third embodiment of the memory device, which shows another function of the CPU 10 as a power supply capacity detection means, the CPU 10 is connected to the engine I/F 15 and the controller I/F of the printer engine 2.
Information regarding the power supply capacity is input from the CPU 4B via F47.

Its structure is the same as the first embodiment shown in FIG.

This is because in the third embodiment, information stored in advance in a ROM (not shown) of the printer engine 2 is input from the CPU 46 instead of reading from the power information setting means 50 in the second embodiment.

If cpUlo inputs the information of the printer engine 2 when detecting the power supply capacity, the subsequent processing may be performed in the same manner as in the second embodiment.

As explained above, according to the present invention, the same controller 1 can be used when the printer system is changed or used for a different printer, and the controller 1 can be supplied from the connected printer engine! If the power supply capacity changes, the power supply capacity detection means detects the power supply capacity, and if a DRAM board etc. is added and the mounting capacity of all DRAMs changes, the mounting capacity detection means detects the mounted capacity, and the refresh current is determined by the power supply capacity. The number of divisions of the installed capacity is set to the minimum within a range that does not exceed , and refresh is performed for each area in which the entire DRAM is divided according to the number of divisions, so the time required for refresh is minimized and performance is improved. .

Although an example in which the present invention is applied to a printer has been described above, the present invention is not limited to printers.
It can also be applied to OA equipment, etc., for which DRAM boards and expansion/replacement boards equipped with DRAM are available as options.

〔Effect of the invention〕

As explained above, according to the present invention, there is no fear that a refresh current exceeding the power supply capacity will flow, corresponding to the installed capacity of the DRAM or the power supply capacity supplied, and a memory equipped with a DRAM that performs refreshing with good performance. equipment can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of first and third embodiments of a memory device for a printer according to the present invention, and FIG. 2 is a timing chart showing an example of a refresh cycle thereof. FIG. 3 is a block diagram showing the configuration of the second embodiment. FIG. 4 is a block diagram showing an example of the configuration of a controller using the same memory device. 1... Controller (printer controller) 2...
・Printer engine (connection device that supplies power 3)
・Host machine 4...Operation panel 10...-CP
U (mounted capacity detection means, power supply capacity detection means, information input means) l 3-RAM l 4・VRAM18...
Expansion RAM 20...DRAM device 21...D
RAM 30...Refresh device 31...
Refresh division number control section 32...Refresh control section 33...Refresh address counter 34...Refresh/RAS generation section 50...Power information setting device (power information setting means) Fig. 1 Fig. 3

Claims (1)

[Scope of Claims] 1. A memory device equipped with a DRAM whose mounting capacity can be changed by attaching and detaching a part of the DRAM, comprising: a mounting capacity detection means for detecting the mounting capacity of the DRAM; and a mounting capacity detection means for detecting the mounting capacity of the DRAM. area setting means for dividing the DRAM into one or more areas according to the mounting capacity detected by the means; and the DR for each area divided by the area setting means.
A memory device equipped with a DRAM, characterized in that it is provided with refresh means for refreshing an AM. 2. In a memory device equipped with a DRAM that can selectively connect devices with different power capacities that can be supplied to the memory device, detecting the power capacity that can be supplied to this memory device from the connected devices. power supply capacity detection means; region setting means for dividing the DRAM into one or more regions according to the power supply capacity detected by the power supply capacity detection means; and for each region divided by the region setting means. Said DR
A memory device equipped with a DRAM, characterized in that it is provided with refresh means for refreshing an AM. 3. By selectively connecting devices with different power supply capacities that can be supplied to this memory device and further attaching and detaching a part of the DRAM, the mounting capacity can be changed.D
A memory device including a RAM, comprising: a power supply capacity detection means for detecting the power supply capacity that can be supplied to the memory device from the connected device; a mounting capacity detection means for detecting the mounting capacity of the DRAM; and the mounting capacity. region setting means for dividing the DRAM into one or more regions according to the mounted capacity detected by the detection means and the power supply capacity detected by the power supply capacity detection means; The DR for each area
A memory device equipped with a DRAM, characterized in that it is provided with refresh means for refreshing an AM. 4. A memory device equipped with a DRAM according to claims 2 and 3, further comprising power information setting means for setting information on power that can be supplied from the connected device to the memory device, 1. A memory device equipped with a DRAM, characterized in that said power supply capacity detection means detects a power supply capacity based on power supply information. 5. A memory device equipped with a DRAM according to claims 2 and 3, further comprising an information input means for inputting information from the connected device, and the power supply capacity is determined by the information input means based on the information input from the device. A memory device equipped with a DRAM, characterized in that the detection means detects a power capacity that can be supplied from the device to the memory device.