JPH03181225A - Externally synchronizing programmable device - Google Patents

Abstract

PURPOSE:To easily realize an externally synchronizing system with a small number of parts by inputting both external and internal signals to a phase comparator in order to produce the signals showing the gain or the loss of phases the external and internal signals. CONSTITUTION:A voltage control oscillation circuit 6 produces a signal S3 having an oscillation frequency fZ corresponding to the voltage of a signal S0 outputted from a low pass filter 5. A 1/N frequency dividing circuit 1a divides the signal S3 down to 1/N and outputs an internal signal S2. A phase comparator 3 detects the difference of phases between both signals S1 and S2, and a signal corresponding to the phase difference is outputted from a charge pump circuit 4. Furthermore the signal S0 integrated by the filter 5 is outputted. This feedback control is automatically repeated so that the phase difference between the external signal S1 and the internal signal S2 is set at zero and the external synchronization is attained to the signal S1. Thus it is possible to easily obtain an externally synchronizing system with a small number of parts.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention enables a circuit designer to easily realize or modify any circuit according to desired circuit specifications, and also enables a The present invention relates to an externally synchronized programmable device capable of so-called externally synchronized operation in which an internal circuit is operated in synchronization with the phase and frequency of the externally synchronized device.

[Conventional technology]

Conventionally, programmable logic devices have been used as devices that allow circuit designers to easily realize or modify circuits according to desired circuit specifications.
Logic devices) are known.

This programmable logic device can realize an appropriate logic circuit with an AND-OR two-stage configuration by programming appropriate lattice points of the AND matrix and the OR matrix, and can also change the circuit by changing the program. Since it is also possible to redesign, it has excellent functions in terms of versatility.

In addition, programmable logic devices do not only realize random logic, but also realize arbitrary sequential circuits by feeding back the output of the above-mentioned OR matrix or the output of the built-in flip-flop to the input side of the AND matrix. Therefore, it is suitable for use in control devices such as sequential controllers, various measuring instruments, and the like.

Conventionally, a programmable logic device having a configuration as shown in FIG. 8 has been common. That is, in FIG.
In the figure, an input signal line, ~L, consisting of a group of vertical lines, and a product term line, ~lo, consisting of a group of horizontal lines arranged to intersect these input signal lines, and each intersection portion of these lines. A logical product matrix 1 that can realize an arbitrary logic circuit by appropriately programming the lattice points formed in It is provided with a logical sum matrix (functionally represented by multi-input logical sum gates OR, ~OR, in the figure) which is connected via an AND gate. Further, general-purpose input ports 11 to IJ for supplying logic circuits from the outside to some input signal line groups among the input signal lines L1 to L1, and clock input terminals cLK for supplying clock signals, i = logic. An output port for outputting the output signal of the sum matrix (multi-input OR game!-0RI to 0R3 in the figure) to the outside, and a control signal for supplying a control signal for controlling the output timing of the output port. An input terminal CNT etc. are provided.

The configuration of the output port can be described as a representative output circuit related to the output terminal P, as shown by the logical sum (indicated by OR3 in the figure).
The output is a D-type flip-flop FF.

The output contact Q is connected to the output terminal P1 via the output sofa circuit B+.

Further, the clock input contact of the flip-flop FF is wired so that the clock signal is supplied from the clock input terminal via the input buffer circuit, and the output buffer circuit B1 receives the control signal supplied from the control signal input terminal CNT. Depending on the logic level of the signal, the output signal of the flip-flop FF is transferred to the output terminal P, or placed in a high impedance state. Furthermore, flip-flop FF.

The inverted output Q is routed to the human power signal line via the bumper circuit FB+, and is wired so as to be fed back to some of the human power signal line groups of ~L1. The output circuits related to the remaining output terminals P2 to P also have a similar configuration, and for example, these output circuits are formed in a cell structure.

By programming appropriate lattice points of the AND matrix, the aforementioned flip-flops formed in the output circuit form shift registers, counters, etc., and at the same time, by feeding back the output to the AND matrix, complex Sequential controllers and various signal processing circuits can be realized.

[Problem to be solved by the invention]

By the way, it is known that an effective technical method for sequential controllers and signal processing circuits is to control various devices and perform signal processing by synchronizing the phase and frequency to follow the phase and frequency of a certain signal. ing.

According to this technical method, when two or more systems operate in synchronization with different frequencies, the phase of the signal transferred from one system is By operating the other system so as to follow the same frequency, the other system can be operated synchronously with respect to one system.

As a typical technical means for performing such so-called external synchronization, PLL (phase-1oc
kedloop) is known, and as an example of its application,
Applications include motor speed control systems, FM/AM transmission/reception systems, and measuring instruments that extract only the desired signal from noise, and PLL devices are being developed as ICs (integrated circuits).

However, conventional PLL devices were developed as dedicated devices for various applications, so
It is necessary to select a specific PLL device depending on the application, and a separate PLL device is required to make changes to the system.
There are problems such as inconveniences such as not being able to find a suitable PLL device to implement a desired system, and a low degree of freedom in system design.

The present invention was developed in view of such conventional problems, and allows external synchronization operation, and allows a circuit designer to easily realize or change any circuit according to desired circuit specifications. The purpose is to provide a highly versatile externally synchronized programmable device.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a programmable logic section having an AND matrix and an OR matrix for realizing an arbitrary logic circuit by connecting appropriate lattice points in a program, and a programmable logic section having an AND matrix and an OR matrix, and A phase that compares the phase of the signal and the internal signal formed by the logic circuit, outputs a signal indicating the delay or lead of the phase, and transfers the output to a predetermined signal input line of the AND matrix. The present invention is a programmable IC device that includes at least a comparison circuit.

[Effect]

According to the present invention having such a configuration, by manually inputting an external signal supplied from the outside and an internal signal generated in an internal circuit realized by an internal programmable logic section to the phase comparator, the external signal and the internal signal are input to the phase comparator. Since it is possible to generate a signal indicating a phase delay or lead between internal signals,
An externally synchronized system in which feedback is applied to the internal circuit so that the signal indicating the phase delay or lead reaches a predetermined value can be easily realized with a small number of parts. Further, since the programmable logic section can form any circuit by programming appropriate lattice points, the degree of freedom in design is high and changes can be easily made.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

First, the structure will be explained based on FIG. - In this example, it is formed as a single IC (integrated circuit device) using a CMO3 semiconductor process, and the input signal lines L1 to L1, which are made up of vertical lines in the figure, and these human input signal lines are An arbitrary logic circuit can be realized by providing product term lines l, ~l, . . . consisting of a group of horizontal lines arranged to intersect, and by appropriately programming the grid points formed at each of these intersections. A conjunctive matrix 1 that can be used, and a product term line 1. -42. It is equipped with a disjunctive matrix (functionally indicated by a multi-input disjunction gate OR, ~ORi in the figure) connected via a logical AND output (functionally indicated by an AND gate in the figure) made from ing. Further, general-purpose input terminals 11 to I4 for supplying logic signals from the outside to some input signal line groups of the input signal lines -L, control signal input terminals CNT for supplying control signals, etc. is provided. Then, the OR matrix (multi-input OR gates ORt~OR, in the figure)
Multiple output terminals P1 for outputting output signals to the outside
An output port with ~Pi is formed.

To describe the output circuit related to the output terminal P1 of the output port as a representative, the logical sum (indicated by OR0 in the figure) output is D.
The output contact Q is connected to the output terminal P+ via the output cover circuit B+. Further, the clock input contact of the flip-flop FF is wired so that a clock signal is supplied from the clock input terminal via the input buffer circuit, and the output buffer circuit B+ is connected to the control signal supplied from the control signal input terminal CNT. The output signal of the flip-flop FF is output to the output terminal P according to the logic level of the signal.
1 or put it in a high impedance state. Furthermore, the wiring is such that the inverted output Q of the flip-flop FF is fed back to a part of the input signal line group of the input signal lines L1 to L via the buffer circuit FB. The output circuits related to the remaining output terminals P2 to P also have a similar configuration, and for example, these output circuits are formed in a cell structure.

Furthermore, 2 is an oscillation buffer connected between the input/output terminals O8I and OSz, and a reference clock signal can be formed by internal oscillation by connecting an external crystal resonator or RC circuit for oscillation, or Alternatively, the external clock signal is input directly from O31 and input to the clock input (CK) of the internal flip-flop.

3 is a phase comparator circuit which outputs an external signal S input via an input terminal In+ and a logical sum output OR.

Alternatively, the phases of the internal signals 32 from the output terminals (in this embodiment, the inverted output terminal ?:i) of the flip-flop FF are compared, and a signal representing the phase difference is output.

A charge pump circuit 4 outputs a pulse width modulated digital signal corresponding to the signal output from the phase comparison circuit (digital phase comparator in this embodiment) 3 to an output terminal Pn+.

FIG. 2 shows a specific circuit example of the phase comparison circuit 3 and charge pump circuit 4. That is, the phase comparator circuit 3 is a digital phase comparator circuit composed of a plurality of NAND gates and inverter gates, and as shown in FIG. A logic output signal SLI and a logic output signal So having a time width corresponding to the phase difference are output, and when the phase of the external signal S is advanced with respect to the internal signal S2, the logic output signal Su is at "L" level, and the internal signal External signal S for S2
When the phase of I is delayed, the logic output signal S becomes "H" level.

On the other hand, the charge pump circuit 4, as shown in FIG.
Power supply contact - Formed by a P-channel MO3 type transistor and an N-channel MO3 type transistor connected between DD and the ground contact, a logic output signal Su is supplied to the gate contact of the P-channel MO3 type transistor, and the N-channel MO3 type Logic output signal S at the gate contact of the transistor.

These common node contacts are connected to the output terminal Pn.

Therefore, when the logic output signal S is at the "L" level and the logic output signal SIl is at the "L" level, an output S at the "H+t level" is generated, and the logic output signal So is at the "H" level.
When the logic output signal So is at the "HI+" level, an output SP at the "L" level is generated, and in other combinations, the output terminal Pn+ is set in a high impedance state except in a transient state.

FIG. 4 shows a circuit configuration when the externally synchronized programmable device of the embodiment having such a structure is applied to a PLL. That is, the part indicated by the dotted circle in FIG. 4 is the external same jJI type programmable device related to this embodiment, and by programming appropriate lattice points of the AND matrix 1 (see FIG. 1), 1/ This realizes an H frequency divider circuit 1a. As an external circuit, as shown in the figure, a low-pass filter (lag lead filter) 5 consisting of a resistor and a capacitor is connected to the output terminal Pn+, and a crystal oscillator and variable A voltage controlled oscillation circuit 6 including an amplifier 2 is constructed by connecting a capacitive diode, a resistor, a capacitor, etc., and the output signal S0 of the low-pass filter 5 is connected to an input contact of the voltage controlled oscillation circuit 6.

According to the PLL circuit configured in this way, the voltage controlled oscillation circuit 6 generates the signal S3 of the oscillation frequency r2 corresponding to the voltage of the signal S0 output from the low-pass filter 5, and
The frequency dividing circuit 1a receives this signal S.

The internal signal S2 is output by dividing the frequency by 1/H. and,
A phase comparator circuit 3 detects a phase difference between an external signal SI and an internal signal S2, a signal corresponding to the phase difference is output from a charge pump circuit 4, and a signal S is further integrated by a low-pass filter 5. is output.

By automatically repeating the feedback control in this PLL circuit, the PLL circuit operates so that the phase difference between the external signal S1 and the internal signal S2 becomes zero, and external synchronization with respect to the external signal S1 is realized.

According to this specific example, by programming appropriate lattice points of the AND matrix 1 (see FIG. 1), a 1/H frequency divider circuit 1 having an arbitrary frequency division ratio N according to the program is created.
By realizing the above, it becomes possible to easily set the frequency of the signal S2 applied to the phase comparator circuit 3, which increases versatility and greatly improves the degree of freedom in design.

Furthermore, in contrast to this, in conventional IC-based PLL devices, the frequency dividing circuit is composed of a binary counter with a fixed number of bits, and the number of bits used and the number of counts (frequency division ratio) of the binary counter can be set to multiple numbers. Although the number of settings is limited, it is possible to realize multiple types of frequency dividing circuits by making selections at the input terminals. Therefore, in the past, even if it was implemented as an IC, many external terminals were required to set this frequency division ratio, and there were restrictions on the upper limit of the frequency division ratio, so functions were reduced. Limited to devices. However, according to this embodiment, by programming appropriate lattice points of the AND matrix 1 (see Figure 1), the frequency divider circuit and other circuits can be realized and changed easily. It is not necessary to externally set the counter value, and the limit on the number of settings for the division ratio of the frequency divider circuit has been greatly improved, so it is more versatile and has more freedom in design than before. It is possible to provide a device that can significantly improve the

Next, another embodiment will be described with reference to FIG. First, to explain the configuration, the differences in FIG. 5 from the previous embodiment shown in FIG. 1 are as follows: In addition to the logical product matrix 1 and logical sum matrix, etc., which can realize any logic circuit by programming grid points, and the pre-fixed phase comparison circuit 3 and charge pump circuit 4, the voltage controlled oscillation circuit 7 and an active filter 8 are built in in advance, and the entire device is integrated into an IC.

The phase comparator circuit 3 and the charge pump circuit 4 are constructed from a circuit similar to that shown in FIG. 2, and are wired so that the external signal S is supplied from the input terminal In+, and the internal signal S! The wiring is such that it is supplied from the programmable matrix section as in the previous embodiment.

The voltage controlled oscillation circuit 7 is, for example, a circuit as shown within the dotted line in FIG. 6, and is composed of a transistor, a diode, a resistor, etc., and a capacitor C of an appropriate capacity is connected between the input/output terminals O3 and O32. By connecting , it is possible to generate a signal S3 of a desired frequency with respect to the voltage level of the signal S0. Note that the signal S0 is the output of the active filter 8, and the signal S3 is the output of the AND matrix 1.
It is wired so that it is supplied to CLOCK.

The active filter 8 is composed of an amplifier 9 and a resistor as shown, for example, within the dotted line in FIG. By connecting
A low-pass filter having desired frequency characteristics can be realized.

Then, by connecting appropriate lattice points of the AND matrix 1 by a program to form a frequency dividing circuit with an appropriate frequency division ratio, a PLL can be easily realized.

According to this embodiment, since the basic parts of the phase comparison circuit, charge pump circuit, active filter, and voltage controlled oscillation circuit are built-in, the number of external components can be reduced when realizing the PLL.

In addition, the logical product matrix l can realize any other logic circuit, and by changing the program, it is also possible to realize a PLL with other characteristics, and the degree of freedom in design can be greatly improved. .

In addition, in the above two embodiments, the case of manufacturing by applying the CMOS process was explained, but it is also possible to apply the B1-CMOS process and form internally a phase comparator circuit etc. that can process analog signals. good.

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a programmable logic section having an AND matrix and an OR matrix for realizing an arbitrary logic circuit through program connections, and an output connected to a predetermined signal input line of the AND matrix. In addition, it is formed by at least a built-in phase comparison circuit that compares the phase of an external signal and an internal signal formed by the logic circuit and outputs a signal indicating a delay or lead in the phase. An externally synchronized system in which feedback is applied so that the signal indicating the phase between the signal from the internal signal and the internal signal reaches a predetermined value can be easily realized with a small number of parts.

Further, since programmable logic having a logical product matrix can form any circuit by programming appropriate lattice points, the degree of freedom in design is high and changes can be easily made.

In particular, it can be an extremely effective means for realizing PLL.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing the structure of an embodiment according to the present invention; Fig. 2 is a circuit diagram showing a specific circuit example of a phase comparison circuit; Fig. 3 is an operation of the phase comparison circuit shown in Fig. 2. Figure 4 is a circuit diagram when one embodiment is applied to a PLL circuit; Figure 5 is an explanatory diagram of the configuration of another embodiment; Figure 6 is a diagram showing the configuration of another embodiment; A circuit diagram showing a specific configuration of a voltage controlled oscillator circuit; FIG. 7 is a circuit diagram showing a configuration of an active filter of another embodiment; FIG. 8 is an explanatory diagram of a conventional example configuration showing the configuration of a conventional programmable logic device. be. Symbols in the figure: 1: AND matrix la; 1/N frequency divider circuit 2; amplifier 3: phase comparison circuit 4; charge pump circuit 5; low-pass filter 6; voltage-controlled oscillation circuit 7; voltage-controlled oscillation circuit 8; Active filter 9; Amplifier (outer side, Figure 3, right) Figure 6

Claims (1)

[Claims] A programmable logic unit having an AND matrix and an OR matrix that realizes an arbitrary logic circuit through program connections, and a programmable logic unit that compares the phase of an external signal and an internal signal formed by the logic circuit. What is claimed is: 1. An externally synchronized programmable device comprising at least a built-in phase comparator circuit that generates a signal indicating phase lag and phase lead.