JPH03181289A - time division switching device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a time-sharing method for exchanging voice or data, etc., between terminals used in digital electronic exchanges, digital key telephone main devices, etc. Relating to a switching device.

BACKGROUND OF THE INVENTION FIG. 4 shows the configuration of a time division switching device used in a conventional digital electronic exchange or the like.

In FIG. 4, 1 is an input highway, and the time-sharing information transmitted through the input highway 1 is addressed by the highway number (physical location) and time slot number (temporal location). Call memory 2
accumulated within. Reference numeral 3 denotes a maintenance memory, which stores exchange connection information from a main control circuit 4 that controls overall call processing of the entire device such as a digital electronic exchange through an external interface unit 5. The exchange connection information instructs which time slot number of which highway number of the output highway 6 the time division information stored in the communication memory 2 is to be outputted to. Based on this exchange connection information, the time division information stored in the call memory 2 is output to the output highway 6 at a specific output timing. 7 is time sharing information on input highway 1 and output highway 6;
and a clock/frame signal generation unit that synchronizes the holding memory 3 and the call memory 2.

Next, the operation of the above conventional example will be explained. As shown in FIG. 5, the time division information on input highway 1 is divided into time slot numbers TSI, TS2 .
Time-sharing data AO, BO, CO, on TS3 and TSn.
. . 20, and time-sharing data AI, B1, C1, . This time-sharing data AO, BO, CO...
・ZOlAl.

As shown in FIG. 6, Bl, C1...Zl are generated by the clock frame signal generator 7 in the call memory 2, where the lower part of the address corresponds to the highway number and the upper part to the time slot number. It is accumulated sequentially in synchronization with the input timing.

Now, as shown in FIG. 7, the lower part of the address corresponds to the output highway number, and the upper part corresponds to the time slot number. Assume that a number has been written. Now, when the output highway number (lower) and time slot number (upper) are output as read addresses to the holding memory 3 according to the output timing from the clock/frame signal generation unit 7, the data stored in the holding memory 3 is output as the read address of the call memory 2. Call memory 2
As a result of this address input, the stored time-sharing information is changed to a different order from that on input highway 1, as shown in FIG. 5, namely BO, Bl, Al...Dl, AO.
, CI, EO...CO to the output highway 6.

In this way, even in the conventional time division switching device described above, the main control circuit 4 rewrites the stored data (input highway number, time slot number) in the holding memory 3 through the external interface unit 5 based on call control information from the terminal. By doing so, time-sharing information can be exchanged freely.

Problems to be Solved by the Invention However, in the above-mentioned conventional time division switching device, time division information (IS) that has meaning across multiple time slots is
When exchanging DN Ho channels, etc.), there is a problem in that time ordering cannot be ensured. This will be explained using FIGS. 8 and 9. FIG. 8 shows a case where the time order of the time division information is ensured, and FIG. 9 shows a case where the time order is not ensured. In Figures 8 and 9, the input highway time slot)/7
0. It is assumed that the time division information AI and A2 on /71 are meaningful data together in the same frame (time). As shown in FIG. 8, the order relationship of the time slots of the input highway and the output highway is no<n2. /7+<n
In case 3, time ordering is ensured. However, as shown in FIG. 9, the order relationship of time slots is no<
n2. If nI > /73, the data of A2 is 771
>773, so time slot n3 of output highway
output timing (call message readout timing)
is earlier than the input timing of time slot /71 of the input highway (timing of writing into the call memory), so the time-sharing information A2 within the same frame cannot be exchanged.
The time division information A2-1 in the previous frame is exchanged and output, making it impossible to ensure time order.

The present invention is intended to solve such conventional problems, and aims to provide an excellent time division exchange device that can ensure time order in time division exchange.

Means for Solving the Problems In order to achieve the above object, the present invention provides a one-frame delay section and an output highway selection section between the speech memory and the output highway, and also sets a normal/delay switching flag in the holding memory. In addition, the holding memory and the output highway selection section are connected by a normal/delayed switching signal to ensure the time order of the output time-division information.

Effects The present invention has the following effects due to the above structure. That is, by providing a one-frame delay unit and an output highway selection unit between the communication memory and the output highway in the time division exchange device, the time order of a plurality of time division exchanged information can be maintained. If not, the time-sharing information that was exchanged in advance in time is transferred by a one-frame delay unit.
In addition to being able to delay by a frame, the output highway selection unit can select undelayed time division information and delayed time division information to output the time division information to the output highway.

The selection of time division information by the output highway selection section is determined by the normal/delay switching signal from the holding memory. This signal is generated by the normal/delay switching flag in the holding memory at the timing of reading data from the holding memory (timing of outputting the read address to the call memory), and is output to the output highway selection section.

Embodiment FIG. 1 is a schematic block diagram showing the configuration of an embodiment of the present invention. In Figure 1, 11 is the input highway, 12
13 is a call memory that temporarily stores the time-sharing information sent from the input highway 11 for exchange connection, and 13 is a storage that stores exchange connection information for changing the order of the time-share information stored in the call memory 12. A memory having a normal/delay switching flag in the memory. 14 is a main control circuit that controls the exchange of time-sharing information; 15 is a main control circuit 1;
4 to the holding memory 13, 16 an output highway, 17 a clock frame signal for synchronizing the time-sharing information on the input highway 11 and the output highway 16, and the holding memory 13 and the speech memory 12; This is the generation part. Reference numeral 18 denotes a one-frame delay unit that delays the time division information output from the communication memory 12 by one frame. Reference numeral 19 denotes an output highway selection section, which selects the output from the call memory 12 (no delay) and the output from the 1 frame delay section 18 based on the normal/delay switching signal 20 at the output timing, and selects the output from the communication memory 12 (no delay) and the output from the 1 frame delay section 18 to the output highway 16. This is the part that is sent. Normal/delay switching signal 2
0 is a signal generated based on the normal/delay switching flag in the holding memory 13.

Next, in the operation of the above embodiment, a process in which time-sharing information is exchanged while ensuring time order will be described. As shown in FIG. 2, the exchange connection information written from the main control unit 14 to the holding memory 1.3 using the output highway number and time slot number as addresses is normal/delayed in addition to the input highway number and time slot number. It shall have a switching flag. The normal/delay switching flag is output from the holding memory 13 at the time of outputting the time-sharing information, and generates a normal/delay switching signal. The input timeslot value is greater than the output timeslot value.

The time division information outputted from the call memory 12 at the output timing is input to the output highway selection section 19 without being delayed, and after being delayed by one frame by the one frame delay section 18. Output highway selection section 19
Now, with the normal/delayed switching signal, the exchange of time-sharing information for which time ordering cannot be ensured in the conventional example shown in FIG. By outputting the data to the output highway 16 with a one-time delay, it is possible to perform exchange while ensuring time order. That is, in the conventional example shown in FIG. 9, since the output time slot number n3 is smaller than the input time slot number n1, the frame time division information A2-1 of the previous jJk-1 is the current frame jlik frame. If the time division information A1 is entered after the time division information A1, the time order will be disrupted, but in this embodiment, the time division information A2-
The time-sharing information A1-1 of the previous frame No. 1, which is the same as No. 1, is also taken into the current frame No. 1, thereby ensuring time order. As a result, both A1 and A2 on the call memory will be sent to the next frame, so in the next +1 frame, A1 and A2 will be sent to the next frame.
will be output while maintaining the temporal order.

In this manner, according to the above embodiment, the time-sharing information exchanged in advance in time is delayed by one frame in the one-frame delay unit 18, and is output by the normal/delay switching signal from the holding memory 14. Since the highway selection unit 19 selects the non-delayed time-sharing information and the delayed time-sharing information and outputs them to the output highway 16, multiple pieces of time-sharing information are output while ensuring time order. There is an effect that can be achieved.

Effects of the Invention As is clear from the above embodiment, the present invention provides a 1-frame delay section and an output highway selection section between the call memory and the output highway in the time division switching device, and also provides a time order in the holding memory. A normal/delayed switching flag is provided to determine the necessity of ensuring quality, and a signal based on this normal/delayed switching flag selects the output highway between the speech memory output delayed by one frame and the speech memory output without delay. By selecting and outputting the information in the section, it is possible to exchange time-sharing information that requires time-ordering in a time-sharing manner while ensuring time-ordering.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a time division exchange device according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a holding memory in the same device, and FIG. 3 is a diagram showing a mode of time division data exchange in the same device. 4 is a schematic block diagram of a conventional time division switching device, FIG. 5 is a diagram showing time division data of the same device, and FIG. 6 is a diagram showing the configuration of a call memory in the same device.
FIG. 7 is a diagram showing the structure of the holding memory in the same device, FIG. 8 is a diagram showing a mode of time-sharing data exchange in the same device, and FIG. 9 is a diagram showing another mode of time-sharing data exchange in the same device. FIG. 11... Input highway, 12... Call memory, 1
3... Holding memory, 14... Main control circuit, 15...
- External interface section, 16... output highway,
17... Clock/frame signal generation section, 18...
1 frame delay section, 19... output highway selection section,
20...Normal/delay switching signal.

Claims (1)

[Claims] A one-frame delay section and an output highway selection section are provided between the speech memory and the output highway, and a normal/delay switching flag for determining the necessity of ensuring time ordering is provided in the holding memory, and this normal/delay switching is performed. A time division switching device in which the output highway selection unit selects and outputs time division information from the call memory and the one frame delay unit based on a signal based on a flag.