JPH03181296A - Pulse reception circuit for object identification system - Google Patents

Abstract

PURPOSE:To attain a communication at a close distance by inhibiting the communication at a side lobe part. CONSTITUTION:When a reception coil L2 obtains a reception signal, a leading detection circuit 31 detects the leading at a time t1 and a threshold level Vref1 is given to a comparator 34. A signal from a decoder 25 is outputted at a time t1 when the count of a counter 24 reaches 2 and the reception signal and the threshold level Vref1 are compared. When the phases of them are opposite to each other, a reception inhibit circuit 36 receives an output and the reception is inhibited afterward and no reception output is obtained. In this case, the output of a flip-flop 28 is inverted at a time t3 when a timer 27 expires. The reception signal when a main beam is transited after a time t5 has an inverted phase after the time t1 and even with the output of the decoder 25, the level does not reach the threshold level Vref1 and no phase discrimination output is obtained. Thus, when the phase is normal, the signal is received based on the signal sent from a data carrier as it is.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an article identification system used for the management of tools of machine tools, parts and products in factories, or distribution systems, and particularly relates to the pulse receiving circuit thereof. be.

[Conventional technology]

As a conventional article identification system, for example, Japanese Patent Application Laid-Open No. 64-713
As shown in Japanese Patent No. 96, an apparatus has been proposed in which data is transmitted between a write/read control unit and a data carrier using pulses. FIG. 4 is a block diagram showing the overall configuration of such a conventional article identification system.
is connected. Pulse transmitting circuit 2 and pulse receiving circuit 3
A transmitting coil Ll and a receiving coil L2 are provided respectively. A data carrier 5 having a resonant circuit including a coil L3 is attached to the article, and is mounted on a pallet or the like of a conveyance line (not shown) to hold the data of the article.

[Problem to be solved by the invention]

As shown in FIG. 5(a), the write/read control unit having the pulse transmitting/receiving circuit configured as described above has a transmission area A in which data can be transmitted from the read/write head 4 to the data carrier. Similarly, area B of the reception area where the signal from the data carrier 5 can be received is
is possible. The data carrier 5 is shown in FIG. 6(a).
, (b), there are positions where reception is possible, and if the position of the data carrier 5 changes, the direction of the magnetic flux applied to the receiving coil L2 is reversed. Therefore, side lobes as shown in FIG. 5 are generated, but the phase of the side lobes is reversed. Therefore, the communication area where transmission is actually possible is the area where the transmission area A and the reception area B overlap, as shown in Part 6 (b). When a data carrier approaches in front of a read/write head that has such a communication area and passes on line 11, communication may occur partially at the sidelobe position, and the data carrier may partially communicate at the position of the side lobe, just before entering the main beam. A communication error occurs because communication is interrupted.

Therefore, if the read/write head and the data carrier are brought closer than a predetermined distance, stable communication cannot be achieved. Therefore, it is necessary to set the distance between these lines to a predetermined value or more, as in line 12, for example, which has the disadvantage that the range of communicable distance becomes narrow.

The present invention was made in view of the problems of the conventional article identification system, and it solves these problems by prohibiting communication based on the fact that the phase is reversed in the sidelobe portion. The technical problem is to solve the following.

[Means to solve the problem]

The present invention provides a pulse receiving circuit for an article identification system that is provided adjacent to a pulse transmitting circuit that alternately sends out positive and negative pulses from a transmitting coil, and receives data based on the period of the positive and negative pulses obtained in the receiving coil. A counter that counts the pulses obtained in the receiving coil when receiving data, a decoder that determines a predetermined count value of the counter, and a phase that determines the phase of the received signal obtained when receiving data given the output of the decoder. The device is characterized in that it includes a discrimination circuit and a reception prohibition circuit that prohibits reception based on the discrimination output from the phase discrimination circuit.

[Effect]

According to the present invention having such features, the pulse receiving circuit counts the signals obtained in the resonant circuit using a counter when receiving data, and when the counted value reaches a predetermined value, the phase discrimination circuit is activated. ing. The phase discrimination circuit discriminates the phase based on the received signal of the received output, and if it is a side lobe, a signal with the opposite phase to the received signal in the main beam is being received, so reception is prohibited.
If the phase is not reversed, data is received based on the period of the pulse without inhibiting reception.

〔Example〕

FIG. 1 is a circuit diagram of a read/write head 4 comprising a pulse transmitting circuit 10 and a pulse receiving circuit 20 of such an article identification system. In this figure, the pulse transmitting circuit 10 has a buffer 11 as in the conventional example described above, and its output is sent to a pair of P-channel and N-channel MO3FETs 12.1 through capacitors C1 and C2.
Given to the gate of 3. FETs 12 and 13 are connected to the power supply Vc
connected in series between C and ground. FET12゜1
A transmitting coil L1 is connected in series between the ground terminals at the intermediate connection point of each drain of No. 3 via a capacitor C3.

A resistor R1 is installed between the gate and source of FET12 and FET13, respectively.
, R2 are connected. Resistors R1 and R2 constitute a short-time time constant circuit together with capacitors CI and C2, respectively, and provide a minute-time pulse signal to FET 12 or 13 at the rise and fall of the clock signal given from buffer 11. . Now, "1" given from outside
The signal is applied to the gate of FET 14 that constitutes an inverter. The drain of FET14 is P channel MO9
It is connected to the respective gates of FETs 15 and 16, and its source end is grounded. The source of the FET 15 is connected to the power supply terminal, and the drain is connected to the gate of the FET 12.

Further, the source of the FE 716 is connected to the power supply terminal, and the drain is connected to the common connection terminal of the FETs 12 and 13 via a resistor R3. Also, the reset signal is N-channel MO3FET17
．． Given to 18 gates.

FET17 is connected between the gate of FET13 and ground, and FET18 is connected to FET12,1 through resistor R4.
It is connected between the common connection end of 3 and ground.

Further, in the pulse receiving circuit 20, a resonance capacitor C4 is connected to the receiving coil L2, and an FET 21 is connected to the receiving coil L2 via a resistor R5.
is connected between the ground terminals. Now, the output of the resonant circuit is given to the amplifier circuit 22.

The amplifier circuit 22 amplifies the received high frequency signal, and its output is given to one input terminal of an exclusive OR circuit (referred to as an EOR circuit) 23.

The output of the EOR circuit 23 is given to a counter 24. The counter 24 is, for example, a quinary counter, and provides its counting output to a decoder 25 and its overflow output to an OR circuit 26. The OR circuit 26 provides the output of the timer 27 and its OR output to the flip-flop 28.

The flip-flop 28 is a flip-flop that is set and reset by the rising edge of the input signal, and its Q output is given to the buffer 11 mentioned above and transmitted to the ID controller as received data. Further, the Q output of the flip-flop is given to the other input terminal of the EOR circuit 23. Here, the timer 27 generates a timing signal with a period longer than the period of the pulse sent out from the pulse transmitting circuit 10. Further, when the count output of the counter 24 is a predetermined number (for example, 2), the decoder 25 supplies the output to the phase discrimination circuit 30. The 0 phase discrimination circuit 30 detects the rise and fall of the count output of the flip-flop 28. 31 and 32, and their respective outputs are given to a threshold determination circuit 33. The threshold determining circuit 33 sets the thresholds Vrefl and Vref2 at predetermined positive and negative levels based on the zero level based on the output thereof, and the output thereof is given as a reference input to the comparator 34. Further, the output of the decoder 25 described above is given to the analog gate circuit 35 as a control signal. The analog gate circuit 35 provides the output of the amplifier circuit 22 to the comparator 34 while the output from the decoder 25 is provided. The comparator 34 is for comparing the output at the moment of time with the dark value, and when it is larger than the threshold value Vrefl,
If it is smaller than 2, a comparison output is given to the reception inhibiting circuit 36. The reception inhibiting circuit 36 is an off-delay timer that operates for a certain period of time based on the comparison output, and its output is given as a control signal to the FET 21 connected in parallel to the resonant circuit.

Next, the operation of this embodiment will be explained. First, during transmission, a transmission pulse is given to the pulse transmission circuit 10 at a constant cycle, and the FETs 12 and 13 are alternately driven to cause the pulse current at that time to flow through the transmission coil Ll. A signal is transmitted to the data carrier 5 by alternately repeating these positive and negative pulses. Further, during reception, the timing at which the positive and negative pulses are sent is determined when the counter 24 reaches a predetermined count value, and the flip-flop 28 is inverted to provide the next positive or negative pulse to the pulse transmitting circuit 10. Now, Fig. 2(a) shows this flip-flop 28.
is the output signal of , and the rising or falling time t of the output is
+, j1ts, a transmission pulse is output from the transmission coil L1 as shown in FIG. 2(b). Therefore, if there is a nearby data carrier, the reverberation signal generated in the resonant circuit of the data carrier causes the receiving coil L of the pulse receiving circuit 20 to
2, a received signal as shown in FIG. 2(C) is also obtained.

Also, the rising edge detector 31 of the phase discrimination circuit 30 detects time 1.
The rising edge of .degree. is detected, and the first threshold value Vrefl as shown in FIG. 2(C) is thereby selected and applied to the comparator 34. At time t2 when the count value of the counter 24 becomes "2", the decoder 25 outputs a signal as shown in FIG. 2(d) based on the count output. Therefore, a comparison is made by the comparator 34 via the analog gate circuit 35 to determine whether the received signal exceeds this threshold value Vrefl.

If it is assumed that a signal exceeding this threshold value is obtained by the output of the resonant circuit when the count output of the counter 24 becomes 2 in the opposite phase, a comparison output as shown in FIG. 2(e) is obtained. Since this signal is given to the reception prohibition circuit 36, from then on, the resistor R5 is connected in parallel to the resonant circuit, and reception is prohibited, and almost no reception output is obtained as shown in FIG. 2(C). . In this case, timer 2
At time t when 7 times up, a signal is transmitted to the flip-flop 28 via the OR circuit 26, and the output of the flip-flop 28 is inverted. At time t, the output of the flip-flop 28 is inverted, causing the signal ``to fall'' and a transmission pulse as shown in FIG. 2(c) to be obtained. In this case, the fall detector 32 sets the dark value to a threshold value Vref2 that is lower than the zero level.

Similarly, at time t4, when the counter 24 counts 2, the signal passing through the analog gate circuit 35 becomes less than the threshold Vref2, and a phase discrimination output as shown in FIG. 2(e) is obtained. Therefore, in this case also, Fig. 2(f)
As shown in , reception is prohibited for a predetermined period of time.

Now, if the data carrier 5 moves from the side lobe of the receiving area to the main beam side after time t, such a phase will not be reversed. That is, if the output of the flip-flop 28 rises at time t, it causes
) is obtained. At this time, the phase of the received signal is reversed from that after time t1 as shown in FIG. 2(C), and even if there is an output from the decoder 25, it does not reach the threshold Vrefl and no phase discrimination output is obtained. Therefore, reception is not inhibited, and the output of the amplifier circuit 22 is directly converted into a square wave and counted. The counted value of the counter 24 is set to the predetermined value (“5” in this embodiment).
Then, the overflow output is transmitted to the flip-flop 28 via the OR circuit 26, and the overflow output is transmitted to the flip-flop 28 through the OR circuit 26.
8 is reversed. Therefore, when the phase is normal, reception is performed based on the signal directly transmitted from the data carrier.

If the signal returns to the opposite phase side, reception is similarly prohibited.

In this way, the present invention can prevent side lobes occurring in the read/write head, so as shown in FIG. 3(a),
As shown in (b), only the portion of the main beam where transmission area A and reception area B overlap becomes a communication area. Therefore, even if the data carrier is brought close to the read/write head, no communication error occurs, and stable data communication can be performed.

[Effects of the Invention] As described above, according to the present invention, data transmission is enabled only in the main beam portion by prohibiting data transmission in opposite phases during reception. Therefore, mobile communication is possible even at short distances, and the distance between the read/write head and the data carrier can be reduced to improve the stability of communication.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a read/write head according to an embodiment of the present invention, FIG. 2 is a time chart showing its operation, and FIG. 3 is a diagram showing a communication area of the read/write head according to this embodiment. FIG. 4 is a block diagram showing the overall configuration of a conventional article identification system, FIG. 5 is a diagram showing the signal transmission area and communication area of a conventional read/write head, and FIG. 6 is a diagram showing a state where the phase is reversed. be.

Claims (1)

[Claims] (1) A pulse receiving circuit of an article identification system, which is installed adjacent to a pulse transmitting circuit that alternately sends out positive and negative pulses from a transmitting coil, and receives data based on the period of positive and negative pulses obtained from a receiving coil. a counter that counts pulses obtained by the receiving coil when receiving data; a decoder that determines a predetermined count value of the counter; and a phase of a received signal that is given the output of the decoder and obtained when receiving the data. A pulse reception circuit for an article identification system, comprising: a phase discrimination circuit that discriminates; and a reception prohibition circuit that prohibits reception based on a discrimination output from the phase discrimination circuit.