JPH0318180A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To generate same V, H clear signals as those obtained from an analog synchronizing separator circuit by obtaining the V, H clear signals from a digital component signal. CONSTITUTION:A detection circuit 2 detects and outputs a start (EAV) of a horizontal blanking period and field odd even information from a timing reference signal of an input digital signal. The signals are inputted to a DFF 3, its output signal (c) is inputted to a selector 5 directly through a 1/2 delay circuit and the width of an odd number field and that of an even number field are made equal to each other. The obtained signal is inputted to a DFF 6 and an EXNOR circuit 7, the edge is detected and an active low v pulse is obtained. The V pulse is inputted to a switching circuit 8 together with an active low H pulse from the circuit 2. The switch 8 selects anyone of analog and digital signals as a synchronizing reference signal.

Description

TECHNICAL FIELD The present invention relates to a sync separation circuit, and more particularly to a sync separation circuit used in a digital television video signal processing device.

CCIR is used as a digital component video signal system in a conventional digital television video signal processing device.
There is a 4:2:2 system that complies with the 801 recommendation.

The synchronization separation circuit in this type of television video signal processing apparatus employs an analog type, and therefore, as a reference signal therefor, an analog signal of a system different from the video system is used.

In this way, in conventional video signal processing systems, since the synchronization separation circuit is of an analog type, it is necessary to prepare an analog synchronization signal in a separate system from the video system. It has the disadvantage that it cannot be used as a reference signal.

Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks of the prior art, and its purpose is to obtain V and H clear signals from digital component video signals, thereby achieving analog synchronization. It is an object of the present invention to provide a synchronization separation circuit that can produce signals equivalent to V and H clear signals obtained from the separation circuit.

Structure of the Invention The synchronization separation circuit according to the present invention includes means for generating a horizontal retrace synchronization detection signal synchronized with the start timing of the horizontal retrace interval from a timing reference signal of a digital component video signal, and means for generating a horizontal retrace synchronization detection signal synchronized with the start timing of the horizontal retrace bright interval, and means for generating a field signal whose level is alternately inverted for each field based on the horizontal blanking period detection signal; means for delaying the field signal by half the horizontal scanning period; means for alternately selecting a field signal in synchronization with the field signal; and generating a pulse signal having a pulse width equal to the pulse width of a sampling clock of the digital component video signal in synchronization with the level transition timing of the selected output. The pulse signal is a vertical clear signal, and the horizontal retrace period detection signal is a horizontal clear signal.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

From input terminal 1, Y component and C component are time-division multiplexed.
A digital component video signal of bits is input manually and enters the timing reference signal detection circuit 2.

The timing reference signal detection circuit 2 detects the start of the horizontal retrace period (EAV: Cnd of Act1ve) from the timing reference signals added to the beginning and end of H blanking of the manually input digital component signal.
Vldeo) and field odd-even information are detected and output. The waveforms of these signals are shown in Figure 2(a). Each is shown in (b).

A signal detecting field odd-even information is sent to the data input side of the D flip-flop 3, and a signal detecting the start of the horizontal retrace period is sent to the clock input side of the D flip-flop 3. The output waveform of the D flip-flop 3 in this case is as shown in FIG. 2(C), and is a signal that is low in an odd field and high in an even field.

This signal is divided into two systems, one system passing through the 1/2H delay circuit 4 and the other system directly being sent to the selector 5. The directly sent system is also used as a control signal for the selector 5. This output signal becomes as shown in FIG. 2(d). In other words, the edge of the field odd-even signal for an even field is 1/
By shifting by 2H, the widths of the odd and even fields become equal.

The edge of the signal thus obtained is detected by the D flip-flop 6 and the exclusive NOR gate 7 whose clock is 13.5MH2 (sampling clock frequency of the digital component signal), and the edge is detected as shown in FIG. 3(e). An active low V pulse is obtained. This V pulse is sent to the switch 8 together with the active low H pulse obtained by the timing detection circuit 2.

Further, as outputs of the analog synchronization separation circuit, ■, clear and H clear are input to the other side of the switch 8. The output of the switch 8 is inputted to a reference synchronization signal generation circuit (not shown). This switch 8 allows selection of either an analog signal or a digital signal as a reference signal for synchronization.

Figure 3 shows the timing reference signal detection circuit 2 in Figure 1.
FIG. The timing reference signal has 4 words added at the beginning and end of the H blanking period, and the FF.
00.00. It is a 4-word sequence called XY, where XY has line information. The 8 bits of XY are as shown in FIG. 4, and the field information F is the second bit from the MSB, and outputs "0" when it is an odd field and "1" when it is an even field.

In FIG. 4, the information V at the third bit from the MSB becomes "1" during the vertical retrace period and "0" during the video data period.
”.The 4th bit information H is E A V (End
or Active V1deo) becomes '1'', and S A V (Start or Active V
ldeo) becomes MO”.

Referring to FIG. 3, in the 8-man powered NAND gate 11, a low signal is output only when the input signal is FF;
It is delayed by one stage by the flip-flop 15. In the nine-man powered NAND gate 12, a low signal is output only when the input signal is 00 and the previous stage is an FF, and this is delayed by one stage in the D flip-flop 16.

Furthermore, in the 9-man powered NAND gate 13, the input signal is 00, and the previous stage is 00, the two previous stages are 00, and the two previous stages are FF.
The 2nd and 4th bits are checked from the MSB of the human input signal at the time of , and - is output only when both are high.

That is, of the timing reference signals added at the beginning and end of the H blanking period, the first one, that is, E
AV (End of Actlvi Video
), the field information is checked, and a row is output only when the field is an even number. The output signal is active low and has a width of 1 clock (37 ns: pulse width of the sampling clock of the digital component video signal)
becomes the pulse of

Note that the circuit surrounded by the broken line is PLA (Prog
raIInable Log1c Array).

In this way, the horizontal blanking period detection signal (a) and the field odd-even information (b) are outputted from the output terminals 18 and 19, respectively.

Effects of the Invention As explained above, according to the present invention, it is possible to perform synchronization separation from the digital component signal, so the digital component signal can be used as a reference signal for the synchronization signal, and therefore, the input video signal By using this as a reference, there is an effect that video signals can be transferred without worrying about the t-order relationship between devices.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is an operational waveform diagram of each part of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram showing an example of the timing reference signal detection circuit of FIG. FIG. 4 is a diagram showing line information of the timing reference signal for each bit. Explanation of symbols of main parts 2... Timing reference signal detection circuit 3.6...
...D flip-flop 4 ...1/2H delay circuit 5 ...Selector 7 ...Exclusive NOR gate Fig. 1

Claims (1)

[Claims] (1) means for generating a horizontal retrace synchronization detection signal synchronized with the start timing of a horizontal retrace period from a timing reference signal of a digital component video signal; means for generating a field signal whose level is alternately inverted; means for delaying the field signal by half a horizontal scanning period; and alternately outputting the delayed output and the field signal in synchronization with the field signal. and means for generating a pulse signal having a pulse width equal to the pulse width of the sampling clock of the digital component video signal in synchronization with the level transition timing of the selected output, and converting the pulse signal into a vertical clear signal. A synchronization separation circuit characterized in that the horizontal retrace period detection signal is a horizontal clear signal.