JPH03181990A - Switching controller for display memory - Google Patents

Abstract

PURPOSE:To improve profitability by performing the data read of a ROM and the data write and read of a DRAM(dynamic random access memory) on a time-division basis. CONSTITUTION:The display memory 13 composed of the DRAM and the ROM 15 are connected to a display control circuit 12 through a common bus line 17. Then the data read of the ROM 15 and the data write and read of the display memory 13 are performed in order on a time-division basis. Therefore, the ROM 15 and DRAM 13 which differ in access system can be used as display memories respectively; and the constitution is simple and an increase in the number of pins of an IC-implemented display control circuit can be suppressed. Consequently, the reduction in cost is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a display memory switching control device that selectively switches between two types of display memories with different access methods.

(Prior Art) As is well known, display data such as character data obtained by receiving teletext broadcasting, characters or graphic data created using a microcomputer, etc., is displayed on a color television receiver's cathode ray tube. An image display system that displays images on a (cathode ray tube) screen has been developed.

FIGS. 4 and 5 show such conventional image display systems. First, in the system shown in FIG. 4, display data created by a microcomputer 11 is sent to the DRA via a display control circuit 12 formed into an IC (integrated circuit).
M (dynamic random access memory) is written to the display memory 13, and then the display memory 1 is
The image is read out from 3 and displayed on a display device 14 such as a cathode ray tube via a display control circuit 12.

In this case, the display control circuit 12 includes a ROM (read only memory) 15 in which fixed display data such as instruction manuals are recorded, and a RAM (random access memory) used for arithmetic processing by the microcomputer 11. ) 16 are connected. And display control circuit 1
2 writes the fixed display data read from the ROM 15 into the display memory 13, reads it again from the display memory 13, and displays the image on the display device 14.

Moreover, what is shown in FIG.
has built-in ROM11a and RAMI1b,
A case is shown in which fixed display data is written in this ROM 11a.

By the way, in the above-mentioned conventional image display system, when the amount of fixed display data increases, it takes a long time to transfer the fixed display data from the ROM II, lla to the display memory 13. This causes the inconvenience that display cannot be performed. Therefore, conventionally, ROM1.1, in which fixed display data is recorded,
11. Use a as it is as display memory, and R
OM11. .

It has been considered to omit the operation of transferring fixed display data from the display memory 11a to the display memory 13 to speed up the image display operation.

However, when ROMII and lla are used as display memory, the access methods are significantly different between ROMII and lla and the DRAM that constitutes the original display memory 13.
2 and the bus line for connecting the DRAM and the display control circuit 12 must be installed in separate systems, which complicates the configuration and makes it difficult to use an IC. The problem arises that the number of bins in the display control circuit 12 increases, which is economically disadvantageous.

(Problem to be solved by the invention) As described above, a ROM in which fixed display data is recorded
The conventional method of using the display memory is
With ROM and DRAM that constitutes the original display memory,
Since the access methods are significantly different, it is necessary to install separate bus lines for each, which increases the number of pins in the IC-based display control circuit, which is economically disadvantageous. .

Therefore, the present invention has been made in consideration of the above circumstances, so that even if ROM and DRAM with different access methods are used as display memories, the I/O can be realized with a simple configuration.
An object of the present invention is to provide an extremely good display memory switching control device that can suppress the increase in the number of bins in a C-based display control circuit and make it economically advantageous.

[Configuration of the Invention (Means for Solving the Problems) A display memory switching control device according to the present invention includes a DRA
M and display device are connected, and the human-powered display data is displayed on D.
The object of the present invention is a display system having a display control means for recording data in a RAM, converting the data into data suitable for display on a display device, and reading the data to the display bag holder. And DRAM
A ROM connected to a common bus line with the DR and in which predetermined fixed display data is recorded;
generating means for generating address data to be supplied to the AM;
The ROM address data generated by this generation means and D
The device is equipped with a selection means for selectively leading out RAM address data to a common bus line, and is configured to time-divisionally execute data read from the ROM and data write and read from the DRAM.

(Function) According to the above configuration, the DRAM and ROM can be connected to the display control means via a common bus line, so that the ROM and DRA which have different access methods can be connected to the display control means.
M can be used as a display memory, and the structure is simple, and even if the display control means is made into an IC, an increase in the number of pins can be suppressed, which is economically advantageous.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, parts that are the same as those in FIG. 12, and read and write data to and from the display memory 13;
The difference from the conventional method is that the reading operation of fixed display data from the ROM 15 is performed in a time-sharing manner.

FIG. 2 shows the display control circuit 12, display memory 13 and R
A specific example of the connection state with OMI 5 is shown. That is, the display control circuit 12 includes a timing generation circuit 18.
is provided. This timing generation circuit 18 is a C.I.C.
A.S.

It generates various control signals such as WR, DOE, RAS/C8 and OE.

Furthermore, one address generation circuit is provided within the display control circuit 12. This address generation circuit] 9 is the DR
Generate AM address and ROM address respectively.
It has trb. Then, the row (Row) address and column (Co 1 umn) of the DRAM address
The address refers to the selection signal s1 that is supplied to each selector 20 and output from the timing generation circuit 18.
It is designed to be selectively derived based on the following.

On the other hand, the above ROM address A. ~14 is address AO
-7 are supplied to the selector 21 together with the output of the selector 2o, and addresses A8-14 are supplied to the ROMI 5 via the first address bus line 17a. Then, the selector 21 selects the output of the selector 2o and the address A based on the selection signal s2 output from the timing generation circuit]8. 7 to the display memory 13 and RO through the second address bus line 17b.
This is what is supplied to M15.

Here, data reading from the ROM 15 and writing and reading of data from and to the display memory 3 are performed sequentially in a time-sharing manner. First, as shown in FIG. 3, in the ROM cycle, that is, the data read cycle from ROMI 5, the selection signal s2 of the timing generation circuit 18 becomes H level, and the selector 21 selects the ROM
Select address generation circuit. For this reason, ROMI 5
is all ROM address A. . . . , 4 are supplied. Also, since the RAS/C8 signal goes to L level, the ROM 15 is selected, and since the OE signal goes to L level, the ROMI 5 becomes in a data read permission state.

Therefore, data is read from the ROM 15, and this read data D. 7 pass through a data bus line 17c common to the display memory 13, are supplied to the display interface 23 via the input buffer 22 in the display control circuit 12, and are displayed as images on the display device 14. Also, R.O.
Read data D read from M15. 7 to the microcomputer 11, the manual buffer 2
Read data D output from 2. 7 to the microcomputer 11 via the microcomputer interface 24.

Next, among the DRAM cycles for writing and reading data to and from the display memory, the display memory 1
In the write cycle in which data is written to DRAM 3, first, the selection signal S2 of the timing generation circuit 18 becomes L level, and the selector 21 selects a DRAM address. In this state, the selection signal Sl of the timing generation circuit 18 goes to L level, and with the selector 20 selecting the row address, the display memory 13 fetches the row address at the falling edge of the RAS/C3 signal. After that, the selection signal S2 of the timing generation circuit 18 becomes H level, and with the selector 20 selecting the column address, the display memory 13 fetches the column address at the falling edge of the CAS signal, and the display memory 13 fetches the column address here. A write address is determined.

On the other hand, as the WR signal becomes L level, 0 The display memory 13 is set to write mode.

Therefore, write data D for writing is sent from the microcomputer 11. ~7 is the microcomputer interface 24. It will be written into the display memory 13 via the output buffer 25 and data bus line 17c. In addition, data obtained from external equipment of the teletext receiver is transferred to the import interface 26.
is supplied to the output buffer 25 via the display memory 1.
Written in 3.

Next, in a read cycle in which data is read from the display memory 13 among the DRAM cycles, a row address and a column address are first fetched into the display memory 13 in the same manner as in the write cycle. Also, at this time, since the WR multiplied signal becomes H level, the display memory 1
3 becomes the read mode, and the DOE signal goes to L level, so the display memory 13 enters the data read permission state.

Therefore, data 1 is read from the display memory 13, and this read data D. 7 pass through the data bus line 17c, are supplied to the display interface 23 via the input buffer 22, and are displayed as images on the display device 14. Also, read data D read from the display memory 13. 7 to the microcomputer 11, the read data D output from the manual buffer 22. ~7 to microcomputer interface 2
4 to the microcomputer 11.

Therefore, according to the configuration of the above embodiment, the DRA
Since the display memory 13 and the ROM 15 made up of M can be connected to the display control circuit 12 via the common bus line 17, the ROM and DR which have different access methods can be connected to the display control circuit 12 via the common bus line 17.
A display control circuit 12 which can be used as a display memory and has a simple configuration and is implemented as an IC.
The increase in the number of bins can be suppressed.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[Effects of the Invention] As detailed above, according to the present invention, even if ROM and DRAM with different access methods are used as display memories, the pins of the display control circuit integrated into an IC can be easily realized with a simple configuration. It is possible to provide an extremely good display memory switching control device that can suppress an increase in the number of display memories and be economically advantageous.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a display memory switching control device according to the present invention, FIG. 2 is a block diagram showing a specific example of the main part of the embodiment, and FIG. A timing diagram for explaining the operation of the example, and FIGS. 4 and 5 are block configuration diagrams showing conventional image display systems, respectively. 11... Microcomputer, 12... Display control circuit, 13... Display memory, 14... Display device,
15... ROM, 16... RAM, 17... Bus line, 18... Timing generation circuit, 19... Address generation circuit, 20.21... Selector, 22...
- Human power buffer 3, 23... display interface, 24... microcomputer interface, 25... output buffer, 26... capture interface.

Claims (1)

[Claims] A DRAM (dynamic random access memory) and a display device are connected, and input display data is recorded in the DRAM, converted into data compatible with display on the display device, and read out to the display device. In a display system having a display control means, a ROM (read only memory) connected to a common bus line with the DRAM and in which predetermined fixed display data is recorded, and a ROM (read only memory) that is supplied to the ROM and the DRAM. A generating means for generating address data, and a selecting means for selectively leading out the ROM address data and DRAM address data generated by the generating means to the common bus line, A switching control device for a display memory, characterized in that it is configured to time-divisionally execute data writing and data reading to and from the DRAM.