JPH03182119A - Pll lock detecting circuit - Google Patents

Abstract

PURPOSE:To prevent a lock output from being erroneously outputted during a transient response by generating the lock detection output after the lapse of one period of a reference signal when the input phase of a phase comparator is coincident. CONSTITUTION:A phase comparator 1, a logical gate circuit 2, a first flip-flop circuit 3 and a second flip-flop circuit 4 are provided. When the input phase of the phase comparator 1 is not coincident, namely, when a 'Low' level is generated for one period of the reference signal, the 'Low' level is outputted for one period and when the input phase of the phase comparator 1 is coincident, a clock next to the reference signal outputs a 'High' level. Therefore, when the input phase of the phase comparator 1 is coincident, the lock output is not immediately generated. Thus, the lock detection can be prevented from being erroneously outputted during the transient response.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on PLL (Phase Locked Loo).
p) Regarding circuits, particularly regarding digital PLL lock detection circuits.

[Prior Art] Conventionally, a PLL circuit incorporates a phase comparator for detecting a phase difference between a reference signal and an input signal from a VCO.

FIG. 3 is a schematic block diagram of the PLL circuit, and FIG. 4 is a timing chart showing waveforms from point a to zero in FIG.

The phase comparator 10 uses the input signal b and the VCO 20 (Vo
ltage Controlled 0sc111
ator), and if the phase of the reference signal lags behind the input signal, outputs a negative pulse (0 point signal) with a duty cycle proportional to the phase difference. do.

At this time, the signal d remains at "High". Conversely, if the phase of the reference signal is ahead of the input signal, a negative pulse (signal at point d) is output. At this time, the C signal remains "High". Then, when the phases of the reference signal and the input signal match, c,
d are both at the "High" level.

The output (negative pulse) of the phase comparator 10 is integrated into the integral block 3
0, and then passes through the low-pass filter 40 to convert the digital quantity into an analog quantity (error voltage). This is given to the VCO 20 to control the oscillation frequency of the VCO 20, align the phases of the reference signal and the input signal, and perform this synchronization. Data is extracted from the input signal in the locked state (locked state).

Therefore, it is necessary to detect this locked state.

The logic gate circuit 50 is a circuit for detecting the above-mentioned lock state, and is a logic gate circuit 50 which is a circuit for detecting the above-mentioned lock state, and is a logic gate circuit 50 which is a circuit for detecting the above-mentioned lock state.
By taking D (or NAND), "H1gh@" is output in the locked state, and "Low" is output in the unlocked state (signal at point e).

That is, the phase comparator 10 and the logical gate circuit 50
Configure the LL lock detection circuit.

[Problems to be Solved by the Invention] However, in the above-described PLL lock detection circuit, when the phases of the reference signal and the input signal match, the lock output is immediately output, so there is the following problem.

When the lock is released from the lock state and a lock-in operation is performed to match the phase again, the phase of the input signal (synchronized signal) repeatedly advances and lags around the phase of the reference signal (i.e., synchronization signal). , converges to the phase of the synchronization signal. This transient characteristic has a unique frequency due to the vibration elements of loop gain and damping constant. Therefore, during a transient response, when the synchronized signal passes through a point where the phases match while converging to the phase of the synchronizing signal, a lock output is generated. In other words, there is a possibility that a lock output may be erroneously output when the lock is unstable.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a PLL lock detection circuit that can prevent erroneously outputting a lock output during a transient response.

[Means for Solving the Problems] A PLL lock detection circuit according to the present invention for achieving the above object detects a phase difference between an input signal and a reference signal from a vCO using a phase comparator, and detects this phase error by using a phase comparator. The device for controlling the VCO based on a detection signal includes: a first holding means for holding the phase error detection signal from a detection start point until a rising edge of the next clock of the reference signal;
and second holding means for holding the output of the holding means for each cycle of the reference signal input to the phase comparator.

[Operation] With the present invention having the above configuration, even if the phase comparator instantaneously detects a point of phase coincidence during the lock-in operation, the phase error detection output once detected by the first holding means is used as the reference. By holding the signal until the next clock rise and further holding the output of the first holding means every cycle of the reference signal, the lock detection output can be left unheard for at least one cycle. Therefore, it is possible to prevent lock detection from being issued immediately during a transient response.

[Embodiment] FIG. 1 is a block diagram of a PLL lock detection circuit of the present invention, and FIG. 2 is a timing chart showing waveforms from points a to g in FIG. 1 in chronological order.

In the figure, a phase comparator 1 and a logic gate circuit 2 are the same as those described in the prior art section.

The first flip-flop circuit 3 is a D-type flip-flop circuit, whose reset terminal R is connected to the output terminal of the logic gate circuit 2, whose data input terminal D1 is connected to the power supply, and whose clock input terminal CKI is connected to the output terminal of the logic gate circuit 2. A reference signal is input.

The second flip-flop circuit 4 also uses a D-type flip-flop like the first flip-flop circuit 3, and a reference input signal is input to the clock input terminal CK2.
A data input terminal D2 is connected to the output terminal Q1 of the first flip-flop circuit 3.

That is, this second flip-flop circuit reads whether the output of the first flip-flop circuit is "High" or "Low" at the rising edge of the clock of the reference signal, and if it is "High", it is in the lip state and "Low". In this case, it is output from the output terminal Q2 as an unlocked state.

The operation of the PLL lock detection circuit shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

Now, assume that the phase of the reference signal a is delayed with respect to the input signal b at time T1.

The phase comparator 1 outputs a negative pulse with a duty cycle proportional to the phase difference between the reference signal and the input signal. This pulse appears at point C. This clock pulse is then supplied to the logic gate circuit 2 and a loop circuit (integrator circuit, low-pass filter) not shown.

The negative pulse supplied to the loop circuit is supplied to vCO via an integrating circuit and a low-pass filter, and is used to delay the phase of the input signal. The phase of the input signal is delayed and T
At time point 3, overshoot occurs and the phase of the input signal lags behind the phase of the reference signal. Repeat this delay and advance until T4
The phases match at the point in time.

On the other hand, the negative pulse at time T1 supplied to the logic gate circuit 2 is supplied to the reset terminal R of the first flip-flop circuit 3 through point e, and the output of the output terminal Q1 is referenced to the clock input terminal CK1. The signal remains "Low" until the rising edge of the clock is input. Furthermore, the first flip-flop circuit 3 operates similarly for a negative pulse with a duty cycle proportional to the lagging phase at time T2 and a negative pulse with a duty cycle proportional to the leading phase at time T3. , from time T2 to the rise of the next clock of the reference signal, and from time T3 to the rise of the next clock of the reference signal.

A signal synchronized with this reference signal is input to the data input terminal D2 of the second flip-flop circuit 4. Then, the second flip-flop circuit 4 reads data at the rising point of the reference signal input to the clock input terminal CK2 (signal at point f). At any time from T1 to T3, the data is "Low", and the second flip-flop circuit 4 eventually outputs "L" from the output terminal Q2.

Outputs a signal of “W”.

Next, when the phases match at time T4, the outputs c and d of the phase comparison 1 change to "High", and the output of the logic gate circuit 2 (signal at point e) changes to "High".

This 'High' level output resets the first flip-flop circuit 3, and the reference signal at this time is High.
Since it is at the h' level, the output of the first flip-flop circuit 3 is immediately inverted and becomes the "High" level.

This "High" level output is given to the data input terminal of the second flip-flop circuit 4, and the second flip-flop circuit 4 outputs the "High" level of the input data at time T5, that is, at the rising edge of the next clock of the reference signal. ” and outputs it from the output terminal Q2. Therefore, the lock detection output is output after one cycle of the reference signal has passed after the phases match. As described above, when the input phases of the phase comparator 1 no longer match, that is, when a "Low" level occurs during one period of the reference signal, the first
It outputs a "Low" level during the period, and when the input phases of the phase comparator 1 match, it can output a "High" level at the next rising edge of the reference signal.

Therefore, when the input phases of the phase comparator 1 match, a lock output is not immediately output.

It should be noted that the present invention is not limited to the above-mentioned embodiment;
- Directly e from the reference signal and input signal using an OR circuit.
It is possible to generate a signal at the point of , and it is also possible to operate with negative logic instead of positive logic, and various other design changes can be made without changing the gist of the invention. be.

[Effects of the Invention] According to the present invention, the first holding means holds the predetermined time phase error detection output, and the second holding means holds the output of the first holding means at one of the reference signals. By holding the signal every cycle, it is possible to prevent the lock output from being issued immediately when the input phases match, as in the conventional case. This provides the effect that lock determination can be performed reliably and quickly in a stable lock state.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of FIG. 1, and FIG. 3 is a conventional P
A schematic block diagram of the LL circuit, FIG. 4 is a timing chart diagram of FIG. 3. In the figure, l is a phase comparator, 2 is a logic gate circuit, and 3
4 is a first flip-flop circuit, and 4 is a second flip-flop circuit.

Claims (1)

[Scope of Claims] A phase difference between an input signal and a reference signal from a VCO is detected by a phase comparator, and the VCO is controlled based on this phase error detection signal, wherein the phase error detection signal is detected. a first holding unit that holds the reference signal from the starting point until the next clock rise; and a second holding unit that holds the output of the first holding unit for each cycle of the reference signal input to the phase comparator. A PLL lock detection circuit comprising: a holding means.