JPH0318240B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM telemeter transmitter that corrects a reference value of an output frequency to a predetermined value regardless of the reference value of an input signal.

[Prior Art] Generally, in the case of an FM telemeter system in which a transmitter and a receiver are used in a separated state,
When transmitting a signal containing useful information in the DC component, it is necessary to precisely match the reference level at the transmitter and the reference level at the receiver, that is, the reference value of the modulated signal and the reference value of the demodulated signal at the receiver. need to match.

For this reason, conventional FM telemeter transmitters
When the transmitter is placed in a reference input state, its modulated output frequency is configured to match the frequency obtained by dividing the frequency of a separately prepared oscillator.

When this is used in a telemeter using frequency division multiplexed transmission, the subcarrier center frequency between each channel is different, so it is necessary to have a corresponding oscillator for each channel, making the equipment complicated and large. It had many drawbacks, such as increased power consumption.

To solve this problem, when one oscillator is configured to match each channel, the subcarrier center frequency is generated by changing the division ratio of one oscillation frequency. Therefore, each subcarrier center frequency must be set to be an integral multiple of each other, and the subcarrier center frequency of each channel is limited.

Specifically, when the input reference signal of the transmitter is V/F-converted and output, the reference oscillation frequency from the reference frequency generation source and the V/F-converted frequency are compared at the same time, and the difference frequency is calculated. After determining this, D/A convert it to form an analog voltage corresponding to the difference frequency, and add this formed analog voltage value to the input reference signal to keep the transmission frequency for the predetermined input reference signal constant. was being carried out.

For example, the device described in Utility Model Publication No. 55-100299 performs V/F conversion on a reference input signal, and then sends a frequency-divided signal to the V/F-converted frequency to an AND gate, a signal obtained by dividing the reference clock, and a signal for correction. A clock signal is applied, and the output of the AND gate is input to a counter and counted, and then D/A converted to obtain a signal for correction.

However, the signal obtained by frequency-dividing the reference clock described above cannot help but become a rectangular wave having a period of 1/2 ⁿ of the reference clock. Note that n is an integer.

[Problems to be Solved by the Invention] However, this method generates a rectangular wave having a frequency period of 1/2 ⁿ of the reference clock, and there are many restrictions on the subcarrier center frequency of the transmitting and receiving channels. Moreover, as a result, the signal contains many harmonics, and these harmonics are likely to cause beat disturbances.

[Means for Solving the Problems] The present invention has been made in view of the shortcomings in the conventional example, and its purpose is to enable transmission and reception of multiple channels with one oscillator, and in this case, each Channel subcarrier center frequency is limited
Our goal is to provide an FM telemeter transmitter with a large degree of freedom without any limitations.

In order to achieve the above object, the present invention includes the following configuration as a means for solving the above problems.

That is, an adder that adds the input signal and the correction;
A V/F converter that converts the output of the adder into voltage/frequency, a transmission circuit that frequency modulates the output from the V/F converter and transmits it to the receiver side, and a V/F converter that converts the output of the adder into voltage/frequency.
A frequency dividing circuit that divides the output of the converter into a predetermined frequency, a gate signal generation circuit that is set in synchronization with the frequency division signal of the frequency dividing circuit and outputs a gate signal, and a clock that forms a reference clock signal for correction. A reset circuit that resets the gate signal generation circuit when the number of output clocks from the clock generator reaches a predetermined number when the gate signal generation circuit is set, and a reset circuit that resets the output clock from the clock generator while the gate signal generation circuit is set. The present invention includes a counter circuit that counts a number, and a correction signal output circuit that performs digital/analog conversion on the count value of the counter circuit to convert it into a corresponding analog signal and outputs the same as the correction signal to the adder.

[Operation] In the above configuration, correction can be performed using the divided output of the V/F converter and the reference time formed using the reference clock, and the output frequency can be adjusted regardless of the reference value of the input signal. It can be corrected to a predetermined value.

Therefore, even when a frequency division multiplexing transmission system is used, there are no restrictions on the allocation of the center frequency of each channel's sub-carrier.
With a single clock generator, it is possible to configure the center frequency of the sub-carrier of each channel so that it is not an integer multiple in order to eliminate interference between each channel, and even in this case, automatic correction of each channel is performed. I can do things.

In this way, the sub-carrier frequency is not limited by the oscillation frequency of the reference clock generator, so even when frequency division multiplexing is used, the sub-carrier frequency of each channel is
There is no need to change the oscillation frequency of the reference oscillator depending on the center frequency of the carrier, and an inexpensive and highly accurate crystal resonator can be used as the reference oscillator.

In addition, because the frequency of the sub-carrier signal is divided to accurately measure its period, the frequency of the reference clock for measurement is more accurate than when measuring the sub-carrier signal without frequency division. It is possible to use lower frequencies without lowering the frequency.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the accompanying drawings.

In FIG. 1, 1 is a preamplifier that amplifies the input signal, 2 is an adder that adds the output voltage of the preamplifier 1 and the output voltage of the D/A converter 16, and 3
4 is a V/F converter that frequency modulates the output of adder 2, and 4 is a main carrier FM modulator.

5 is an operation switch for operating the automatic correction circuit, and in this embodiment a lock type switch is used. The state shown in FIG. 1 is the "off" state. Flip/Flip (FF) 6 is set by turning switch 5 on, and
It is reset by the output of gate 13. 7 is a binary counter, which inputs the output signal Cd of the V/F converter 3 while the F.F6 is set, and sets the signal frequency-divided by the Q and _X stages of the binary counter 7 to the F.F8. Supplied as a signal. F.
F8 is set by the rise of the _QX stage of the binary counter 7 and reset by the rise of the output pulse of the AND gate 10.

Reference numeral 9 denotes a binary counter which is controlled by an inverted signal of the output of F.F8 and inputs the binary output of a specific stage to the AND gate 10 using the output of the clock generator 11 as an input signal. AND gate 10 essentially decodes the output of binary counter 9 and outputs a pulse when the count value of binary counter 9 reaches a predetermined set value.

Reference numeral 11 denotes a clock generator, which supplies input signals to the banary counter 9 and the AND gate 12.
12 is an AND gate, which uses the output signal of F.F8 and the inverted signal of the output of the Q _X stage of the binary counter 7 as a gate, and supplies the input pulse signal from the clock generator 11 to the binary counter 15 as an input signal. .

14 is a delay circuit that delays the output signal of the Q _X stage of the binary counter 7 by a time t ₃ ; 15 is a binary counter that receives the output signal of the AND gate 12 and changes the switch 5 from the OFF side to the ON side. It is set by 16 is binary
D/A converts the output signal of the counter 15 into an analog signal and supplies it to the adder 2 as a correction signal
It is a converter.

17 is a monostable multi-vibrator that is triggered by the output pulse of AND gate 13 and outputs a pulse of a constant width. 18 The monostable multi-vibrator 17 is in an "on" state for a certain period of time due to the output, and a constant pulse is sent to adder 2. Analog supply voltage
It's a switch.

FIG. 2 shows a timing chart of the circuit operation of this embodiment having the above configuration. “I” to “NU” in Figure 2 are the same as “I” shown in Figure 1.
It shows the signal timing of each point of ~"nu".

Here, in the circuit of FIG. 1, when the reference input signal is supplied to the preamplifier 1, the V/F converter 3
It is assumed that the operation is performed so that the frequency of the output signal becomes f ₀ , and the following explanation will be given using this f ₀ as the reference output signal frequency.

The operation of the circuit of this embodiment will be explained below with reference to FIG. 2 and a timing chart.

First, a reference input signal is applied to the preamplifier 1.
Next, the operating switch 5 is turned on to generate a trigger signal for circuit operation (FIG. 2a, A). This trigger signal is output for a period of time until the power charged in the capacitor is discharged when the switch is turned off. Since the binary counter 15 is reset by this trigger signal, the output signal of the D/A converter 16 becomes the lowest signal state.

At this time, the output signal from the D/A converter 16 is supplied to the adder 2 at the lowest output state, and the frequency f of the output signal from the V/F converter 3 is at the highest frequency. And D/A converter 1
The frequency f of the output signal of the V/F converter 3 is configured to decrease as the output voltage of the V/F converter 3 increases. Therefore, the frequency of the output signal of the V/F converter 3 when the switch 5 is turned on becomes the highest frequency.

Furthermore, the trigger signal formed by the switch 5 is
At the same time, it is also supplied to F.F6, putting F.F6 in the set state. The output of F.F6 is supplied to the reset terminal R of the binary counter 7 via an inverter. Therefore, when the switch 5 is turned on, the binary counter 7 is placed in the activated state (the second
In FIG. a), the output signal of the V/F converter 3, which has reached the highest frequency state, begins to be accepted as an input signal. The Q _X stage of this vital counter 7 has V/
A signal obtained by frequency-dividing the output signal of the F converter 3 by 1/ ^2X (c in FIG. 2a) is output. Note that the output t ₁ at point C in FIG. 2a is (2 ^x /f).

Then, in synchronization with the rise of this output signal,
F.F8 becomes set state, and when F.F8 is set, binary counter 9 becomes set state (FIG. 2 a, ho) and starts counting using output signal k of clock generator 11 as an input signal. . When _{this count value} reaches { ²⁴ The output of the binary counter 9 and the AND gate 10 are connected as shown in d) of FIG. 2a.
The pulse from AND gate 10 is connected to the reset terminal of F.F8, and the pulse from AND gate 10 is connected to the reset terminal of F.F8.
The F.F8 returns to the reset state in synchronization with the second pulse (FIG. 2a, H).

The output signal of F.F8 obtained in this way has the following:
A time width t ₂ corresponding to a half period of the frequency obtained by dividing the frequency of f ₀ by ( ^1/2
(Ho).

As explained above, t ₁ , which is the output from binary counter 7, and t ₂ , which is the output signal of F.F8, are obtained synchronously, so the difference between these two signals corresponds to the difference in frequency. become. in this way,
Since the reference time is formed by the output of the flip-flop, which is set by the output of the V/F converter and reset when the count value of the reference clock reaches a predetermined value, any frequency can be compared regardless of the clock frequency. It is possible to create a reference signal for Therefore, even if frequency division multiplexing is used and the center frequency of each channel's subcarrier is not an integer multiple of the center frequency in order to eliminate interference between each channel, only one clock generator is required. This allows automatic correction of each channel. Furthermore, since the frequency of the sub-carrier is not limited by the oscillation frequency of the reference clock generator, an inexpensive and highly accurate crystal oscillator can be used as the reference oscillator.

In addition, because the frequency of the sub-carrier signal is divided to accurately measure its period, the frequency of the reference clock for measurement is more accurate than when measuring the sub-carrier signal without frequency division. It is possible to use lower frequencies without lowering the frequency.

Note _{that the} selection of the _Q The desired time width t _{2 may be appropriately selected depending on the value of the desired time width t 2} corresponding to a half period of the frequency divided by ^X ). In this way, this embodiment is configured to be able to select the subcarrier center frequency between arbitrary channels.

On the other hand, the binary counter 15 receives the output signal j from the clock generator 11 during the time period expressed as the difference between t1, which is the output from the binary counter ₇ , and _t2 , which is the output signal from the F.F8. It is counted as an input signal (FIG. 2 a). This count value is output to the D/A converter 16, where it is converted into an analog voltage corresponding to the count value and is applied to the adder 2 as a correction signal.

As a result, the output signal of the V/F converter 3 is corrected so that its frequency becomes slower. During this correction work, the output of the Q _X stage of the binary counter 7 is
It is in the low state and changes to the high state after the correction work is completed. Therefore, the circuit operates again as described above in synchronization with the rise of the output of the _QX stage of the binary counter 7. By repeating this several times, the frequency of the output signal of the V/F converter 3 gradually decreases and approaches the frequency f ₀ of the reference output signal. However, through this repeated operation, the D/A converter 16 and the adder 2 are configured so that the amount of correction is always smaller than the amount corresponding to the time difference. Therefore, the output frequency f of the V/F converter 3 approaches f ₀ even though there is always a time difference of (t ₂ −t ₁ ).

That is, when the frequency-divided output of the binary counter 7 falls after the time _t1 , the binary counter 15 counts the output frequency _f1 of the clock generator 11. Thereafter, when the value of the binary counter 9 reaches a predetermined value, the counting operation of the binary counter 15 is stopped, and the count value of the binary counter 15 is supplied to the D/A converter 16 for correction. This correction operation is performed when the time (t ₂ − _{t 1} ) is a predetermined value (e.g.
t ₃ ) Continue until below. This relationship is the third
As shown in the figure.

And when this time difference (t ₂ − t ₁ ) becomes t ₃ ,
This correction work is stopped.

This leads the output of the Q _X stage of the binary counter 7 to the delay circuit 14, and the delay circuit ₁₄
The signal delayed by the amount of time (T in Figure 2) and the signal for resetting the binary counter 9 are led to the AND gate 13, and when the AND gate 13 is satisfied and becomes high (B in Figure 2). In step (h), F.F6 is reset and the binary counter 7 enters the reset state. At this time F.F8 and binary counter 9
AND gate 12 is also in the reset state.
is no longer satisfied, the binary counter 15 stops counting, and then the operating switch 5
The circuit does not operate and holds the correction signal until is operated.

Note that _t3 is set to a value smaller than the period of the output signal k of the clock generator 11 and larger than the synchronization difference between _t1 and _t2 .

As explained above, in this embodiment, measurement and correction are performed during one cycle of the frequency-divided signal, and measurement is performed in the first half of the cycle and correction is performed in the second half of the cycle, so the correction speed is fast and Since the frequency is not corrected during measurement, accurate correction can be performed.

Furthermore, in this embodiment, the calibration signal is applied to the adder 2 immediately after the series of correction operations described above are completed. In other words, the monostable multivibrator 17 is activated using the pulse of the AND gate 13 as a trigger signal.
A pulse with a constant width is generated, the analog switch 8 is turned on, and an analog voltage corresponding to the calibration signal is applied to the adder 2.

In this way, since the configuration is such that the calibration signal is continuously generated after the automatic correction work is completed, it is possible to confirm that the automatic correction work has been completed on the transmitter side even on the side of the receiver that has been questioned.

As a result, even if an erroneous operation occurs during measurement, it can be confirmed on the receiver side, and if it is recorded, it can be confirmed later when interpreting the measurement results.

In addition, the transmitter and receiver are independent in the correction process, and reference level variations due to transmitter frequency variations are eliminated.

Therefore, by ensuring high accuracy and high stability in the receiver, the telemeter system can more accurately match the output of the reference signal input state to the reference level.

In addition, by having independence, even when the power of the receiver is turned on again, and when multiple transmitters are switched and used with one receiver, the operation is simple and there is no influence on other devices.

The operating switch 5 is a lock type switch or the like, and as shown in FIG. 1, the trigger signal is not generated unless the switch is turned back on and then turned on again, as shown in FIG. Therefore, after a trigger signal has been generated once, at least two actions are required to generate the trigger signal again.

As a result, even if an artificial operation such as accidentally touching a control switch occurs during measurement, correction work does not occur immediately, resulting in trouble during measurement and the troublesome readjustment caused by it, as well as erroneous measurements. can avoid.

Furthermore, since the circuit can be constructed from MOS gates, counters, crystal oscillators for popular watches, etc., it is inexpensive, compact, and has low power consumption, which are favorable conditions for telemeter transmitters.

As explained above, according to this embodiment, the reference time is formed by the output of the flip-flop, which is set by the output of the V/F converter and reset when the count value of the reference clock reaches a predetermined value. It is possible to create a reference signal with which any frequency can be compared, regardless of the clock frequency generated by the oscillator equipped with the oscillator. Therefore, even if the frequency division multiplexing transmission system is varied, there is no restriction on the allocation of the center frequency of the subcarrier of each channel, and each channel can be divided by a single clock generator to eliminate interference between channels. The center frequency of the sub-carrier can be configured so that it is not an integer multiple, and even in this case, automatic correction of each channel can be performed.

In this way, the sub-carrier frequency is not limited by the oscillation frequency of the reference clock generator, so even when frequency division multiplexing is used, the sub-carrier frequency of each channel is
There is no need to change the oscillation frequency of the reference oscillator depending on the center frequency of the carrier, and an inexpensive and highly accurate crystal resonator can be used as the reference oscillator.

In addition, because the frequency of the sub-carrier signal is divided and its period is accurately measured, the frequency of the reference clock for measurement is more accurate than when measuring the sub-carrier signal without frequency division. It is possible to use lower frequencies without lowering the frequency.

Furthermore, measurement and correction are performed during one period of the frequency-divided signal, and the correction speed is fast because measurement is performed in the first half of the cycle and correction is made in the second half of the cycle.Furthermore, since the frequency is not corrected during measurement, it is possible to make accurate measurements. corrections can be made.

Additionally, the circuit includes MOS gates, counters, and
Since it can be configured with a popular crystal oscillator for watches, etc., it can be used as an inexpensive, small, and low-power telemeter transmitter.

Furthermore, a lock-type operation switch is used, and once the correction work is completed, the next time the trigger is generated, the switch is returned once, and then the switch is pressed again.
It has an operation to turn it on. Therefore, the correction work will not be delayed due to human error such as accidentally touching the operation switch during measurement. This avoids trouble during measurement, troublesome readjustment, and erroneous measurements.

Further, since the calibration is performed by continuously generating a calibration signal after the automatic correction work is completed, even the receiver side that has been removed can immediately confirm the completion of the correction work on the transmitter side. This way, even if an erroneous operation occurs during measurement, it can be confirmed on the receiver side, and if it is recorded,
This can be confirmed later when interpreting the measurement results.

In addition, the transmitter and receiver are independent in the correction process, and reference level variations due to transmitter frequency variations are eliminated. Therefore, by ensuring high accuracy and high stability in the receiver, telemeter and
The system can more accurately match the output of the reference signal input state to the reference level.

In addition, by having independence between the transmitter and receiver sides, even if the power to the receiver is turned on again,
Even when multiple transmitters are switched and used with one receiver, the operation is simple and excellent effects can be obtained, with no influence on other devices.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide an FM type telemeter transmitter with a large degree of freedom without limitations or restrictions on the subcarrier center frequency.

Furthermore, one oscillator can support subcarrier center frequencies of multiple channels.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment according to the present invention;
FIG. 2 is a timing chart of each part during the operation of FIG. 1, where part a shows the timing at the start of the operation, and part b shows the timing at the end. FIG. 3 is a waveform diagram for explaining the state in which a correction clock is formed by frequency comparison in this embodiment. Here, 3...V/F converter, 11...Clock generation period, 12, 13...AND gate, 1
5...Binary counter, 16...D/A converter.

Claims (1)

[Claims] 1. An adder that adds an input signal and a correction signal, and a voltage/frequency converter that converts the output of the adder into a voltage/frequency.
an F converter; a transmitting circuit that frequency-modulates the output from the V/F converter and transmits the frequency-modulated signal to the receiver side; a frequency dividing circuit that divides the output of the V/F converter into a predetermined frequency; and the frequency dividing circuit. a gate signal generation circuit that is set in synchronization with a frequency-divided signal of and outputs a gate signal; a clock generator that forms a reference clock signal for correction; and the clock generator that is set when the gate signal generation circuit is set. a reset circuit that resets the gate signal generation circuit when the output clock of the clock reaches a predetermined number; a counter circuit that counts the number of output clocks from the clock generator while the gate signal generation circuit is being set; and a counter circuit that counts the number of clocks output from the clock generator. An FM telemeter transmitter comprising: a correction signal output circuit that performs digital/analog conversion of a value into a corresponding analog signal and outputs the corrected signal to the adder.