JPH0318269A - Precharge circuit - Google Patents

Abstract

PURPOSE:To obtain a stable precharge circuit common to a smoothing capacitor and a power-supply circuit to be combined with each other, by analog-like- controlling the transient ON-state of a precharge resistance short-circuiting FET with an operational amplifier, and by setting control voltage inclination arbitrarily with the constant of a reverse integrating circuit. CONSTITUTION:In the ON-state of a short circuit FET 6, the ON-resistance FET of voltage drop so that an operational amplifier 7 cannot be reversed, is selected, but when any fault is generated and the current of a power-supply circuit 4 is suddenly increased, then the voltage drop of the short circuit FET 6 exceeds the residual minimum voltage of an operational amplifier 18. Then, in order to turn the short circuit FET 6 OFF immediately, a circuit is set to be of high impedance to be determined by a precharge resistor 5. As a result, even when any short circuit fault is generated by the main transistor of the power-supply circuit 4, then the accident of the burning or the like of the circuit can be prevented from being generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switching power supply, and particularly to a precharging circuit for a power supply input capacitor.

[Conventional technology]

An example of a conventional prettage circuit for this type of power supply is shown in FIG. 3 and will be described.

In the figure, 21 is an input power supply, 22 is a switch, 23 is an input smoothing capacitor, and 24 is this input smoothing capacitor 2.
3 is connected in parallel with a switching power supply circuit, 25 is a brightage resistor, 26 is a shorting FET whose source and drain are connected to both ends of this brightage resistor 250, 27.
28 is a resistor, 29 is a detection transistor, and a soener diode 30, a bias resistor 31, and a capacitor 32 are connected in parallel between the collector and emitter of the detection transistor 29. The base of this detection transistor 29 is connected to the precharge resistor 25 via a resistor 27.
The emitter is connected to the other end of the brightage resistor 25, and the collector is connected to the short circuit F through the resistor 28.
It is connected to the gate of ET26. 33 is a bias resistor.

As shown in FIG. 3, the conventional precharge circuit of a power supply has both ends of the precharge resistor 25 connected to the pace of the detection transistor 29, which is a bipolar transistor.
The emitter is connected to the emitter, and the collector is connected to the gate of the precharge resistor shorting FET 26 via the resistor 28.

Figure 4 is a time chart showing the operation of the circuit in Figure 3.
a) shows Suitsute 22! D, (b) is the voltage across the precharge resistor 25, (C) is the collector voltage of the detection transistor 29, (d) is the short circuit FET 26, (
e) is the current Idc flowing through the switching power supply circuit wt24
t is shown. And vT! {1+vTHi
1 indicates the detection voltage.

[Problem to be solved by the invention]

In the conventional precharge circuit described above, since the completion of precharge is detected using the transistor vitg'k, the voltage across the precharge resistor 25 shown in FIG. VB, OF
If it is below F), normal operation will occur, but if the standby bias current of the switch power supply circuit 24 is large (as in B) and does not reach the detection voltage VTH, the FET 26 will not be turned on and the power supply will operate unstable. There was a problem that it would not start or start.

In order to prevent this, the resistance value of the precharge resistor 25 is reduced, but the conventional series type precharge circuit, which rushes in when the switch 22 is turned on, can only be used for extremely limited purposes.

[Means to solve the problem]

The bulletyage circuit of the present invention is a power supply circuit having a large-capacity input smoothing capacitor, and includes a bulletyage resistor connected in series to a parallel circuit of the smoothing capacitor and the power supply circuit, and a source/drain connected to both ends of the bulletyage resistor. e, a first operational amplifier having a negative input connected to the drain electrode of the FET through a first resistor and an output connected to the gate of the FET through a second resistor;
It consists of a second operational amplifier that uses the output of the first operational amplifier as an input and constitutes an inverting and integrating circuit, and the output of the second operational amplifier is connected to the positive input of the first operational amplifier. be.

[For production]

In the present invention, Flli'
The transient ON state of r can be controlled analogously by an operational amplifier, and the control voltage slope can be arbitrarily set using the constant of the inverting and integrating circuit.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a circuit diagram showing one embodiment of a precharge circuit according to the present invention.

In the figure, 1 is the input power supply, 2 is the switch, and 3 (hereinafter referred to as
(referred to as a power supply circuit), 5 is a Briteyage resistor connected in series to the parallel circuit of the smoothing capacitor 3 and the power supply circuit 4;
7 is the source and drain connected to both ends of this precharge resistor 5, and 7 is this FET.The negative input is connected to the drain electrode of 6 through resistor 8, and the output is connected through resistor 9 to FE.
Operational amplifier connected to gate K of T6, 10 is a Zener diode for cranking, 11 is a bias resistor, 12 is a Zener diode, 13, 14, 15.16 is a resistor, 17
1 is an integrating capacitor, and 18 is an operational amplifier which takes the output of the operational amplifier 7 as an input and constitutes an inverting and integrating circuit.The output of the operational amplifier 18 is connected to the positive input κ of the operational amplifier 7.

Then, input power supply 1, switch 2, smoothing capacitor 3,
A main circuit consisting of a power supply circuit 4 and a precharge resistor 5. In the in-loop, resistor 8, crumb Zener diode 10'
A brightage voltage is sent to the operational amplifier γ through fI-, and the output of this operational amplifier 7 is connected to the short-circuit FE through the resistor 9.
The output of this operational amplifier 7 is connected to the input of an inverting and integrating circuit consisting of an operational amplifier 18, a resistor 13, a 14.1516 resistor, and an integrating capacitor 11. The output of is configured to be connected to the positive input terminal of the arithmetic circuit 7.

Figure 2 is a time chart used to explain the operation of Figure 1.
(a) shows the switch 2, (b) shows the voltage across the precharge resistor 5, (C) shows the output voltage of the operational amplifier 18, (d) shows the shorting FET 6, and (.) shows the power supply. The current "dc" (f) flowing through the circuit 4 represents the output of the operational amplifier 7.

In FIG. 2, the voltage across the precharge resistor 5 shown in (a) is the same as the output voltage of the operational amplifier 18, and (b) shows the on-resistance according to the operational amplifier 18. . vTH1 and vTH2 indicate detection voltages.

The operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

1. Time t. Switch 2 is turned on (Fig. 2 (a)
) and the smoothing capacitor 3 is a British resistance 5tl.
- the voltage across this Briteyage resistor 5 (
(see FIG. 2(b)) decreases by the output off voltage (detection voltage) vTRI'' of the operational amplifier 18 at time t0. (VTH
1 uses the output off voltage of the operational amplifier 18 as the detection voltage; in principle, any voltage may be used). When the detection voltage TH0 is reached, the operational amplifier T is inverted, and the driving voltage is applied to the short circuit FET 6, and the inverting and integrating circuit centered around the operational amplifier 18 is operated. decreases to

Since the operational amplifier 7 has a negative feedback configuration for the voltage of the brightage resistor 5, the voltage of the precharge resistor 5 is controlled by the on-resistance change control of the short-circuit FET 6.
The output voltage of the operational amplifier 18 decreases at the same slope as the output voltage of the amplifier 8 (see FIG. 2(c)), and at time t, when the output voltage of the operational amplifier 18 reaches the lowest voltage, it is completely turned on and the prettage is completed.

Then, when the short-circuit FET 6 is in the on state after startup, an on-resistance FET with such a voltage drop that the operational amplifier 7 is inverted is selected, but some kind of failure occurs and the current Idc of the power supply circuit 4 At time t8 when there is a sudden increase (see Fig. 2 (.)), the voltage drop of the short-circuit FET 6 exceeds the residual minimum voltage of the operational amplifier 18, and the short-circuit FET & is immediately turned off (see Fig. 2 (d)). ), because
The circuit becomes high impedance due to the precharge resistor 5, and even if the main transistor of the power supply circuit 4 is short-circuited, accidents such as burnout of the circuit can be prevented.

〔Effect of the invention〕

As explained above, the present invention controls the transient state of the Briteyage resistance short circuit FET using an operational amplifier in a shear analog manner, and the control voltage slope can be arbitrarily set using the constant of the inverting and integrating circuit. A stable precharge circuit can be constructed for both combinations of power supply circuits and power supply circuits, and since the resistance value of the precharge resistor and the detection voltage vTH can be set arbitrarily, it is possible to create a power supply circuit with a large bias current. It is possible to select a high resistance value for , the inrush peak current is small, and use a small, low-power resistor as the bulletyage resistor, making it possible to realize an extremely useful bulletyage circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a precharge circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram showing an example of a conventional precharge circuit. FIG. 4 is a time diagram showing the operation of the circuit of FIG. 3. 3...Input smoothing capacitor (smoothing capacitor), 4
...Switching power supply circuit (power supply circuit), 5...
・Britteyage resistance, 6...Short circuit FET, 7...
...Operation amplifier, 8.9...Resistor, 10...Zener diode for clamp, 11...Bias resistor, 1 2...Zener diode, 13-16...
・Resistor, 17... Integrating capacitor, 18... Operational amplifier.

Claims (1)

[Claims] In a power supply circuit with a large capacity input smoothing capacitor,
a precharge resistor connected in series to the parallel circuit of the smoothing capacitor and the power supply circuit; an FET with a source and drain connected to both ends of the precharge resistor; and a negative input connected to the drain electrode of the FET through a first resistor; It consists of a first operational amplifier whose output is connected to the gate of the FET through a second resistor, and a second operational amplifier whose input is the output of the first operational amplifier and which constitutes an inverting and integrating circuit. A precharge circuit characterized in that an output of an operational amplifier is connected to a positive input of the first operational amplifier.