JPH0318272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory having a chip selection function and comprising a static RAM using insulated gate field effect transistors.

[Prior art]

The following explanation will focus on a MOS transistor (hereinafter referred to as MOST) as an insulated gate field effect transistor, and will focus on a MOS static RAM (random access memory).

FIG. 1 is a block diagram showing the main parts of a conventional MOS static RAM. A plurality of memory cells MC are arranged in a matrix, and selection terminals of the plurality of memory cells arranged in the same row are commonly connected to one word line W1, . . . Wj corresponding to that row. Multiple memory cells arranged in the same column
The data input/output terminals of the MC are commonly connected to the data lines D1, 1 to Dk corresponding to the column. A plurality of data lines Di, are coupled to a common data line via a column switch circuit Y. Word line Wi and column switch input signals Y1,..., Yk are connected to address circuits BX, BY and decode circuits X-DCR, Y-
Selected by DCR. The input terminal of the sense amplifier SA and the output terminal of the data input circuit DIC are coupled to the common data line, and the output of the sense amplifier SA is outputted as a data output D _put via the data output circuit DOB. There are chip selection signals and control signal signals as control signals, and the control circuit
CONT outputs control signals CS' and CS'' that control the selected and unselected state of the chip.The control signal CS' controls the address circuits BX and BY, and when the chip is unselected, the address circuits BX and BY are unselected. Activate.
The control signal CS'' controls the sense amplifier SA and the data output circuit DOB, and deactivates the data output circuit DOB when the chip is not selected.
outputs a control signal WE' that controls writing and reading. During writing, the control signal WE' activates the data input circuit DIC and deactivates the data output circuit DOB. Conversely, during reading, the data input circuit DIC is deactivated and the data output circuit DOB is activated.

In the conventional semiconductor memory circuit shown in FIG. 1, when performing a read operation, the chip is controlled by a chip selection signal, and CS access is performed when changing from a chip non-selected state to a chip selected state, and a chip selection state is performed. There are two types of readout means, one for address access and the other for reading out data when the address input changes, but it is desirable for both to have equal access time in configuring a system or the like. However, in the conventional example shown in Figure 1, the address circuit
BX and BY are fixed in standby state by control signal CS' so that they do not operate when the chip is not selected, so when CS is accessed, control signal CS' becomes active and the address circuit
The disadvantage is that the access time is delayed by the time it takes to activate BX and BY.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory having an address decoding circuit that is controlled so that CS access can be performed at high speed and read stably, by eliminating the above-mentioned drawbacks.

[Structure of the invention]

The semiconductor memory of the present invention includes an address circuit that outputs an address output signal composed of pairs of bits having a mutually complementary relationship corresponding to each bit of an address input signal, and a first circuit that outputs the address output signal. a first decoding circuit that decodes according to the logic of , and outputs a signal in which all bits are at the non-select level when the chip selection signal is at the non-select level; and a second decoding circuit that outputs a selection signal for decoding according to the memory cells and selecting a predetermined one of the plurality of memory cells.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing a main part of an embodiment of the present invention, and shows a decoding circuit that obtains 256 decoded outputs from 8 address inputs.

This embodiment includes an address circuit 1 which outputs an address output signal composed of pairs of bits having a mutually complementary relationship corresponding to each bit of address input signals A1 to A8, and a first decoding circuit 2 which decodes according to a first logic and outputs a signal in which all bits are at a non-select level in response to a control signal CS' when the chip selection signal CS is at a non-select level; A second decoding circuit 3 decodes the output signal of the decoding circuit 2 according to a second logic and outputting signals W1 to W256 for selecting a predetermined one of the plurality of memory cells. Ru.

Address circuit 1 is an address circuit of 8 units.
An address circuit group consisting of AC1 to AC8. Address signals A1 to A8 are input to each address circuit AC1 to AC8, respectively, and a pair of output signals A are complementary to each other depending on the logic level of the signal.
1', 1', A2', 2', . . .

The first decoding circuit 2 is a decoding circuit group consisting of 16 units of decoding circuits 1D1 to 1D16. Here, the outputs of address circuits AC1 and AC2 are decoded by four decoding circuits 1D1 to 1D4, so that four decoded output signals are obtained. That is, decoding circuit 1D1
, signals A1', A that are in phase with address input signals A1, A2 of address circuits AC1, AC2 (hereinafter, signals in phase are referred to as A1', A2') A1', A
Similarly, the decoding circuit 1D2 receives a signal having the opposite phase of A1' and the address input signal A2 (hereinafter, the opposite phase signals are referred to as 1', 2', etc.).
A2' is inputted, 1' and A2' are inputted to the decoding circuit 1D3, and A1' and 2' are inputted to the decoding circuit 1D4. The decoding circuit is
Since it is constituted by an AND circuit, depending on the combination of the logic levels of address input signals A1 and A2, only one of the decoding circuits 1D1 to 1D4 outputs a logic "1" level, and the remaining three outputs a logic “0” level. Similarly address circuit AC
3. The output signals of AC4, AC5, AC6, AC7, and AC8 are sent to decoding circuits 1D5 to 1D8, respectively.
The address input signals (A3, A4), (A
Due to the combination of logic levels of 5, A6) and (A7, A8), only one of each set outputs a logic "1" level, and the remaining three output a logic "0" level. In this way, a total of 16 basic decoding circuits 1D1 to 1D16 of the first decoding circuit 1 are divided into four groups, and only one of each group is configured to output a logic "1" level. .

The second decoding circuit 3 is a decoding circuit group consisting of a total of 256 units of decoding circuits 2D1 to 2D256. Decode circuit 2D1 to 2D256
has a 4-input AND configuration, and one of these four inputs
The input is connected to one of the output terminals of the first set of decoding circuits 1D1 to 1D4 in the first decoding circuit 2, and the other input is connected to one of the output terminals of the second set of decoding circuits 1D5 to 1D8. One input is connected to one of the output terminals of the third set, that is, the decoding circuits 1D9 to 1D12. As mentioned above, since the first decoding circuit 2 has only one output of each set having the logic "1" level, the combination of the logic levels of the address inputs of the second decoding circuit 3, in other words, Depending on the combination of output levels of each set of first decoding circuits 2, only one out of ⁴⁴ outputs a logic "1" level, and the remaining 255 circuits output a logic "0" level. This causes address input signal A
1 to A8, only one of the second decoding circuit outputs W1 to W256 takes the selection level, and this output can be connected to a word line (row selection line) or the like.

Here, the first decoding circuit 2 receives a control signal.
CS′ is input. That is, the control signal CS' is generated inside the chip by a chip selection signal which is an external signal so that it becomes a non-selection level (for example, a logic "0" level) when the chip is in a non-selected state.

In this embodiment, the logic level is set to "1" when the chip is in the selected state, and the logic level is set to "0" when the chip is in the non-selected state. Therefore, by configuring the first decode circuit 2 with an AND circuit of the output signal of the address circuit 1 and the control signal CS', when the control signal CS' is at the logic "1" level, the normal address circuit output is generated. When the signal is decoded and the signal is at the logic "0" level, all the outputs of the first decoding circuit 2 output logic "0" level, that is, non-selection level signals, and as a result, the output of the second decoding circuit 3 All of them are at logic "0" level, that is, non-selected level, and chip selection (selection of word lines, etc.) and non-selected state can be controlled by the above.

Therefore, according to this embodiment, since the control signal CS' is not applied to the address circuit 1, if the logic level of the address input signals A1 to A8 changes at the same time as the chip selection signal enters the selected state,
The address circuit 1 can start its operation without passing over the generation of the control signal CS', and the delay due to CS (chip selection) control in this part can be avoided. And the control signal
At the time when CS′ is added to the first decoding circuit 2,
Output signals A1', 1', A2', 2', . . . of the address circuit 1 according to the address input signals A1 to A8.
also starts to be added at the same time, so CS access can be read out at high speed without any delay in CS control.

Next, a case will be described in which the control signal CS' is input to the second decode circuit 3 instead of the first decode circuit 2. As can be seen from FIG. 2, the signal that has passed through the address circuit 1 and the first decode circuit 2 is applied to the input of the second decode circuit 3. A certain amount of time is required until a signal corresponding to the signal is applied to the second decoding circuit 3. On the other hand, since the control signal CS' is generated by passing through about three stages of inverters in response to the input of the chip selection signal, it is generated in a relatively short time. Therefore, the second decoding circuit 3
When the control signal CS′ is applied to the second
Since the input signal of the decoding circuit 3, that is, the output of the first decoding circuit 2, does not have a level corresponding to the true address input signal, another second decoding circuit 3 is selected according to the erroneous signal. This may result in a lack of stability.

As explained above, by applying the control signal CS' only to the first decoding circuit 2, CS access can be read out quickly and stably, and the load capacitance attached to the control signal CS' can be made relatively small. Therefore, the signal propagation speed can also be increased.

FIG. 3 is a partial detailed circuit diagram of the circuit of this embodiment shown in FIG. 2. Fig. 3 is an example of a circuit configured with complementary MOS transistors, where AC is the address circuit 1, 1D is the first decode circuit 2, and 2D is the second decode circuit.
Each unit circuit of the decoding circuit 3 is shown.
The address circuit AC is composed of three stages of inverters, and outputs an in-phase output signal Ai' and an opposite-phase output signal ' according to the address input signal Ai. Of the three stages of inverters, MOSTQ1, Q3, and Q5 are of P-channel type, and MOSTQ2, Q4, and Q6 are of N-channel type.

The first decoding circuit 1D is composed of a NAND circuit and an inverter. MOSTQ13, Q1
The output signal of the address circuit AC is applied to the gate of No. 4. An output signal j' or ' from another address circuit is applied to the gates of MOSTQ12 and Q15. Further, a control signal CS' is applied to the gates of MOSTQ11 and Q16. MOSTQ11, Q1
2, Q13 is P channel type, MOSTQ14, Q1
5 and Q16 are configured as N-channel type, so when the input signals of the first decoder circuit 1D take the logic "1" level, the P-channel type MOST
Both become non-conductive, and the N-channel type MOST
Since both become conductive, the level of the node N10 connecting the drain of MOSTQ13 and the drain of MOSTQ14 becomes a logic "0" level,
A selection signal, an output signal FDk at a logic "1" level, is outputted to the output node N11, that is, the output terminal of the first decoding circuit 1D, through an inverter constituted by MOSTQ17 and Q18. Conversely, when at least one of the input signals of the first decoding circuit 1D takes a logic "0" level, the node N10 becomes a logic "1" level, and the output node N1
1 is a non-selection signal, a logic “0” level output signal
FDk output.

The second decoding circuit 2D is composed of a 4-input NAND circuit and an inverter. MOSTQ2
4, Q25, Q23, Q26, Q22, Q27,
Separate first decoding circuit output signals FDk, FDl, FDm, FDn are applied to the gates of Q21 and Q28, respectively.
is applied. Since MOSTQ21 to Q24 are of P channel type and MOSTQ25 to Q28 are of N channel type, the first decoding circuit output signal
FDk, FDl, FDm, FDn are all logic “1”
When the level is reached, all P-channel type MOSTs become non-conductive, and all N-channel type MOSTs become conductive, so the connection node N21 between the drain of MOSTQ24 and the drain of MOSTQ25
The level of is a logic “0” level, and MOSTQ2
9 and Q30 to the output node N22, that is, the second decoding circuit 2D.
A selection signal, an output signal W0 of logic "1" level, is outputted to the output terminal of. Conversely, among the first decoding circuit output signals FDk, FDl, FDm, FDn,
When at least one of them takes the logic "0" level, the node N21 becomes the logic "1" level, and the output node N22 outputs the non-selection signal, the output signal W0 of the logic "0" level.

As explained above, according to the circuit shown in FIG. 3, when the semiconductor memory is in the non-selected state, the control signal
CS' provides a first decoding circuit whose outputs both output signals at the non-selection level, and a second decoding circuit whose outputs output signals at the non-selection level accordingly.

Also, although the circuit has been explained above using a complementary type MOST, it is also possible to use an N-channel type MOST or a P-type MOST.
A similar circuit configuration can be made using only MOST.

Note that in the above explanation, address input signals are not distinguished into row address signals and column address signals, but in semiconductor memories, normally the row address input signal causes the selected word line to rise first, and then the selected word line rises after some time. Since data lines and memory cells are selected by a column address input signal, the present invention can be applied to a row address input signal, that is,
Even when applied only to the decoding circuit, a corresponding effect can be obtained in reading CS accesses at high speed and stably.

Further, although the explanation so far has focused on a MOS transistor as an insulated gate field effect transistor, it goes without saying that the present invention can also be applied to other insulated gate field effect transistors.

〔Effect of the invention〕

As described above in detail, the semiconductor memory of the present invention inputs chip selection/non-selection control signals into the conventional address circuit instead of the conventional address circuit, and when the semiconductor memory is non-selected, both outputs are at the non-selection level. Since it includes a first decoding circuit that outputs a signal and a second decoding circuit that decodes the output of the first decoding circuit, it has the effect that CS access can be read out at high speed and stably. ing.

Therefore, by using the semiconductor memory of the present invention, two kinds of accesses can be performed by the reading means: CS access, which is read when the chip is changed from non-selected state to chip selected state, and address access, which is read when the address is changed in the chip selected state. A system with equal time can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a main part of an example of a conventional semiconductor memory, FIG. 2 is a logic block diagram showing a main part of an embodiment of the present invention, and FIG. 3 is a partially detailed circuit diagram thereof. 1... Address circuit (group), 2... First decoding circuit (group), 3... Second decoding circuit (group), 1D, 1D1 to 1D16... First decoding circuit, 2D, 2D1 to 2D256...Second decoding circuit, A1 to A8, Ai, AX1 to AXj, AY
1~AYk……Address input signal, Ai′,′,
Aj′,′……Address output signal, AC1 to AC8,
BX, BY……Address circuit, B1, 1~Bj,
Bj...Data line, CONT...Control circuit,...
Chip selection signal, CS′, CS″…control signal, DIC
...Data input circuit, DOB...Data output circuit,
D _io ...Data input, D _put ...Data output, FDk,
FDl, FDm.FDn...First decoding circuit output signal, MC...Memory cell, Q1, Q3, Q5, Q
11, Q11, Q13, Q17, Q21, Q2
2, Q23, Q24, Q29...P channel type
MOS transistor, Q2, Q4, Q6, Q14,
Q15, Q16, Q18, Q25, Q26, Q2
7, Q28, Q30...N channel type MOS transistor, N10, N11, N20, N21...
Node, SA...Sense amplifier, VCC...Power supply, W
1~Wj...word line, WE'...control signal,
W1 to W256, W0...Second decoding circuit output signal, X-DCR...X decoding circuit, Y-
DCR...Y decoding circuit, Y1-Yk...Y address signal.

Claims (1)

[Claims] 1. An address circuit that outputs an address output signal composed of a pair of complementary bits corresponding to each bit of an address input signal, and an address circuit that decodes the address output signal according to a first logic. and a first decoding circuit that outputs a signal in which all bits are at the non-select level when the chip selection signal is at the non-select level; a second decoding circuit that outputs a selection signal for selecting a predetermined one of the memory cells.