JPH0318274B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a nonvolatile random access semiconductor memory using a nonvolatile semiconductor memory element.

[Prior art]

Traditionally, insulated gate field effect transistors (hereinafter referred to as
It is called IGFET. ) There is a static random access memory (hereinafter referred to as RAM) constructed from a bistable circuit such as a flip-flop circuit using six elements.

By the way, this RAM has the disadvantage that the information stored in the memory cells disappears when the power is turned off or cut off, due to its memory function.
Recently, non-volatile RAM that does not lose information even when the power is turned off or cut off has begun to be provided, but it requires a large number of IGFETs to configure, and it is also difficult to write and erase non-volatile semiconductor memory elements. There was a drawback.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks, reduce the number of IGFETs required for the configuration, make it possible to simultaneously write and erase data to a non-volatile semiconductor memory element,
To provide a non-volatile random access semiconductor memory in which information can be easily read from RAM and in which information does not disappear even when the power is turned off or cut off, and a function that allows writing and erasing using a single 5V power supply. The purpose of the present invention is to provide an additional non-volatile random access semiconductor memory.

[Structure of the invention]

The non-volatile random access semiconductor memory of the first invention includes a bistable circuit having a pair of output nodes, each output node of the bistable circuit being connected to a pair of data lines in a corresponding manner. 1st, 2nd
and a nonvolatile semiconductor memory element whose drain is connected to one output node of the bistable circuit, whose gate is connected to the other output node of the bistable circuit, and whose source is connected to a source power supply. Ru.

Further, the nonvolatile random access semiconductor memory of the second invention includes a bistable circuit, and first and second switch means respectively connected between a pair of output nodes of the bistable circuit and a pair of data lines. , first and second write selection means that are turned on and off by a write selection signal; a non-volatile semiconductor memory element whose sources are respectively connected to the source power supply at the other output node of the bistable circuit through means, and connections between the drain and gate of the non-volatile semiconductor memory element and the write power supply, respectively; the first and second capacitances.

[Description of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the first invention.

In this embodiment, IGFETM1, M2, M3, M4
A bistable circuit 10 constituted by a flip-flop circuit, a pair of output nodes A and B of this bistable circuit 10, and a pair of data lines DL, read out gates serving as switching means connected between each of the bistable circuit 10 and a switching signal terminal X1. Connect the drain to the data line DL,
IGFETM5, M6 whose source is connected to the output nodes A and B respectively in DL, the drain is connected to the output node B of the bistable circuit 10, and the control electrode is connected to the bistable circuit 1.
0 output node A includes a nonvolatile semiconductor memory element Ma1 having a floating electrode whose source is connected to the source power supply V _S .

That is, in this embodiment, one nonvolatile semiconductor memory element Ma1 having a floating electrode is added to the well-known RAM 11 consisting of IGFETs M1 to M6.

Here, the structure and operation of the nonvolatile semiconductor memory element Ma1 having a floating electrode will be explained. FIG. 2 is a schematic cross-sectional view showing the structure of the nonvolatile semiconductor memory element Ma1. In the same figure, 1 is the drain, 2
is a source, 3 is a floating electrode, 4 is a control electrode, 5 is a semiconductor substrate, 6 is a thin insulating film, 7 is a gate insulating film,
8 is a field insulating film.

Taking a nonvolatile semiconductor memory element having an N-channel floating electrode as an example, the drain 1
and the source 2 is an N ⁺ type diffusion region, and the semiconductor substrate 5 is a P
The thin insulating film 6 provided on the mold silicon substrate and the drain diffusion region is, for example, a silicon oxide film with a thickness of 200 Å, and the gate insulating film 7 is a silicon oxide film with a thickness of 1000 Å. Note that this nonvolatile semiconductor memory element having a floating electrode is a known element that utilizes the FN tunneling current phenomenon.

Next, the principle of operation of this nonvolatile semiconductor memory element will be explained.

First, the write operation will be explained. Control electrode 4
The potential of
When V _W (+15V) is applied, a strong negative electric field is applied to the thin insulating film 6 between the floating electrode 3 and the drain 1 when viewed from the drain, and holes are injected into the floating electrode 3 due to the F-N tunnel current. The injected holes are stored in the floating electrode 3, and the floating electrode 3 is kept at a positive potential. As a result, the threshold voltage (hereinafter referred to as _VT ) seen from the control electrode 4 becomes lower. In reality, V _T after writing is approximately -5v. (Initial V _T is about 2v). Note that when the potentials of the control electrode 4 and the drain 1 are both ground potential, no electric field is generated between the floating electrode 3 and the drain 1, so there is no movement of charges.
Therefore, no change in V _T occurs in this state.

Next, the erase operation will be explained. An erase voltage (+15V) is applied to the control electrode 4 to bring the potential of the drain 1 to the ground potential. An electric field in the opposite direction to the write operation is applied, electrons are injected into the floating electrode 3 through the thin insulating film 6, and the potential of the floating electrode 3 becomes a negative potential.
V _T becomes high (V _T 10v).

Figure 3 shows the initial V _T and after writing and erasing.
Indicates the change in V _T. Note that this figure shows the characteristics of the control electrode voltage V _CG and the current _DS flowing between the drain and the source when the potential of the source 2 is set to the ground potential and a constant voltage is applied to the drain 1. The initial V _T , V _{TO ,} is 2V, the V _T after writing, V _TW , is −5v, and the V _T after erasing, V _TE , is 10 V.

Next, the operation of this embodiment using a nonvolatile semiconductor memory element having a floating electrode having such characteristics will be explained.

First, for reading and writing of the RAM 11 consisting of IGFETM1 to M6, the power supply Vc.c. is set to 5V (read voltage), and the source power supply V _S is set to O _V. This results in the same state as when the nonvolatile semiconductor memory element Ma1 is not connected, and reading and writing can be performed in the same way as a normal RAM.

Next, the operation of writing the output information of the RAM 11 into the nonvolatile semiconductor memory element Ma1 will be explained. First, the read switching connection point X1 is set to ground potential. Next, open the source power supply V _S and turn on the power supply Vc.c.
Writing is performed by changing the voltage from 5v to 15v. For example, in the read state, the information at output node A is “0” (ground potential) and the information at output node B is “1”.
(power supply potential). By setting the read switching connection point X1 to the ground potential, this bistable circuit 10 is disconnected from the data line DL. Next, when the power supply Vc.c. is changed from 5v to 15v, the output node A
The potential at output node B changes from 5v to 15v, although the potential remains at ground potential. At this time, since +15V is applied to the drain of the nonvolatile semiconductor memory element Ma1 and the ground potential is applied to the control electrode, writing is performed, and V _T becomes V _TW =-5V. That is, when the output node A is "0", writing is performed in the nonvolatile semiconductor memory element Ma1.

Conversely, the information of output node A in the read state is “1”
(power supply potential) and the information at output node B is "0" (ground potential), when it is in the write state, the ground potential is applied to the drain of the nonvolatile semiconductor memory element Ma1, and +15V is applied to the control electrode. , erasure is performed and V _T becomes V _TE = +10v.

In this way, writing or erasing is performed in accordance with the output information in the read state. This eliminates the need to perform writing and erasing in separate operations, making the method of use extremely simple. Furthermore, even if the power is cut off after writing, the output film is written in the nonvolatile semiconductor memory element Ma1 and is retained semi-permanently.

Next, the operation of reading back the information written in the nonvolatile semiconductor memory element Ma1 to the RAM 11 will be explained. By setting readout switching connection point X1 to ground potential and then increasing power supply Vc.c. and source power supply V _S from O _V to readout voltage 5V,
Reading back to RAM 11 is performed. Consider the case where the above nonvolatile semiconductor memory element Ma1 is being written. When power supply Vc.c. and source power supply V _S are increased from O _V to 5V, the potential of output node A becomes
The potential of the output node B is charged through the IGFET M2 and the non-volatile semiconductor memory element Ma1. At this time, IGFET M
1, M2 and the conductance g _n of the nonvolatile semiconductor memory element Ma1 are g _nM1 , g _nM2 , g _{nMa1 ,} respectively.
By satisfying the condition g _nM1 < (g _nM2 + g _nMa1 ), the charging speed of output node B is faster than that of output node A, and the potential of output node B is equal to that of IGFET M3.
When the voltage exceeds V _T , IGFET M3 is turned on, the potential at the output node A stops rising, and approaches the ground potential, and the potential at the output node B approaches the read voltage. In this way, the potential of output node A becomes “0”
(Ground potential) The potential of output node B becomes "1" (read voltage).

Conversely, consider the case where nonvolatile semiconductor memory element Ma1 is erased. Since the non-volatile semiconductor memory element Ma1 has V _T set to V _TE = +10v, it is always off in the read-back state, the potential of the output node A is charged through the IGFET M1, and the potential of the output node B is Charge through IGFET M2. At this time, by satisfying the condition g _nM1 >g _nM2 , the potential of the output node A becomes "1" (read voltage) and the potential of the output node B becomes "0" (ground potential). In order to enable this read-back, it is necessary to appropriately set the dimensions of IGFETs M1 and M2 so as to satisfy the above two conditions. In this case, it is also necessary to consider the magnitude of the load capacity of the output nodes A and B.

In the above manner, reading/writing to/from the RAM 11 and transfer from the RAM 11 to the non-volatile semiconductor memory element are performed.
Writing and erasing to Ma1 and reading back information from nonvolatile semiconductor memory element Ma1 to RAM11 are realized.

FIG. 4 is a circuit diagram showing a main part of an embodiment of the second invention.

This example uses IGFETs M1, M2, M3, M4
A bistable circuit 10 constituted by a flip-flop circuit constituted by a pair of output nodes A and B of this bistable circuit 10 and a pair of data lines DL, each of which has a gate serving as a switching means connected therebetween as a readout switching connection point. IGFET connected to X1
M5, M6, and the write selection IGFET M7 whose drain is the first write selection means are connected to the output node B of the bistable circuit 10, and whose control electrode is the write selection IGFET M8 whose control electrode is the second write selection means. A non-volatile semiconductor memory element Ma1 has a floating electrode whose source is connected to the output node A of the bistable circuit 10 via the source power source V _S , and the drain of the non-volatile semiconductor memory element Ma1 and the write power source V _PP . and a capacitor C2 as a second capacitor connected between the control electrode C of the nonvolatile semiconductor memory element Ma1 and the write power supply _VPP . consists of things. In addition, IGFET M7, M for writing selection
The gate of 8 is connected to the write selection signal _VWS .
Further, the source of IGFET M7 is connected to the drain of nonvolatile semiconductor memory element Ma1 to form node C, and the source of IGFET M8 is connected to the control electrode of nonvolatile semiconductor memory element Ma1 to form node D. That is, the circuit of this embodiment is constructed by adding write selection IGFETs M7 and M8 and capacitors C1 and C2 to the circuit of the embodiment of the first invention shown in FIG.

Next, the operation of this embodiment will be explained.

First, read/write to RAM11 by using the power supply Vc.c.
Set the write selection signal V _WS to 5v (read voltage)
This is done by setting it to _OV . By setting the write selection signal V _WS to O _V , it is the same as if the nonvolatile semiconductor memory element Ma1 and IGFETs M7 and M8 were separated from the bistable circuit 10, and reading and writing can be performed in the same way as a normal RAM.

Next, the operation of writing the output information of the RAM 11 into the nonvolatile semiconductor memory element Ma1 will be explained.
First, the read switching connection point X1 is set to ground potential. Next, set the write selection signal _VWS to +5v. Furthermore, after setting the source power supply V _S to O _V , the write power supply V _PP is changed from O _V to +15V. By setting the read switching connection point X1 to the ground potential, this RAM 11 is disconnected from the data line DL. For example, consider a case where the information at the output node A in the read state is "0" (ground potential) and the information at the output node B is "1" (power supply potential). By setting the write selection signal _VWS to +5v, the information of the output nodes A and B is taken into the nodes D and C. The potential at node C is (Vc.c.-V _T ), approximately 3V, and the potential at node D is O _V. Next, turn the write power supply V _PP to O _V
When the voltage is changed from +15v to +15v, the potential at node C is pushed up through capacitor C1 and becomes approximately 18v. Also, the potential at node D is pushed up via capacitor C2,
The pushed up charge is discharged through IGFETs M8 and M3 and becomes O _V. At this time, since +18V is applied to the drain (node C) of the nonvolatile semiconductor memory element Ma1 and the ground potential is applied to the control electrode (node D), writing is performed and V _T becomes V _TW =-5V. That is, when the output node A is "0", writing is performed in the nonvolatile semiconductor memory element Ma1.

Conversely, the information of output node A in the read state is “1”
(power supply potential) and the information at output node B is "0" (ground potential), when the write state is entered, the ground potential is applied to the drain of the nonvolatile semiconductor memory element Ma1, and +18V is applied to the control electrode. Erasing occurs and V _T becomes V _TE =+10v. in this way
Writing or erasing is performed in accordance with the output information of the RAM 11 in the read state.

Now consider the write power supply V _PP . The write power supply V _PP needs to be +15V in the write state, but this write power supply V _PP has a capacity of C1, C
It is used only to push up nodes C and D via 2. Since there is no current consumed in this way (the supply current capability only needs to be small), it is possible to use a boost circuit such as a charge pump that generates high voltage within the chip, which is difficult to implement when the current consumption is usually large. . For this reason, by providing a booster circuit inside the chip, it is possible to write and write data using only a single 5V power supply.
Erasure can be achieved.

In this way, there is no need to perform writing and erasing in separate operations, and the method of use is very simple.
Even if the power is cut off after this write operation, the output information is written in the nonvolatile semiconductor memory element and is retained semi-permanently.

Next, the operation of reading back information written in the nonvolatile semiconductor memory element to the RAM will be explained. In this case, by setting the write selection signal _VWS to +5v, the other operations can be carried out in the same manner as in the embodiment of the first invention shown in FIG.

In the above embodiment, a flip-flop circuit composed of six elements was used as a bistable circuit, but the same effect can be obtained even if other bistable circuits are used. Further, although the present invention has been described using an n-channel type IGFET, the same applies to a configuration using a p-channel type IGFET.

〔Effect of the invention〕

As explained above in detail, the nonvolatile random access semiconductor memory of the present invention is configured by including one nonvolatile semiconductor memory element having a floating electrode connected to a bistable circuit, and therefore requires fewer elements. It is possible to store information in a non-volatile semiconductor memory element even if the power is turned off or cut off.
It is possible to store information, and it is also possible to read and write to RAM that includes bistable circuits, write to and erase from non-volatile semiconductor memory elements, and read back from non-volatile semiconductor memory elements to RAM. Each operation is easily performed, and since writing and erasing to the nonvolatile semiconductor memory element are performed at the same time, the method of use is simple and the operating time is halved. Furthermore, by adding a write selection means and a capacitor, a booster circuit is provided within the chip, and writing and erasing can be realized using a single 5V power supply.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a main part of an embodiment of the first invention, FIGS. 2 and 3 are a schematic cross-sectional view and characteristic curve diagram showing the structure of a nonvolatile semiconductor memory element, respectively, and FIG. The figure is a circuit diagram showing a main part of an embodiment of the second invention. 1...Drain, 2...Source, 3...Floating electrode, 4...Control electrode, 5...Semiconductor substrate, 6...
Thin insulating film, 7... Gate insulating film, 8... Field insulating film, 10... Bistable circuit, 11...
RAM, Ma1...nonvolatile semiconductor memory element,
M1, M2... Debretion N-channel insulated gate field effect transistor, M3 to M8... Enhancement N-channel insulated gate field effect transistor, C1, C2... Capacitance, A, B... Output node, C, D... Node, DL, ... data line, Vc.c. ... power supply, V _PP ... power supply for writing, V _S ...
…Source power supply, V _WS …Write selection signal, X1
... Readout switching connection point.

Claims (1)

[Claims] 1. A bistable circuit having a pair of output nodes, and first and second switch means respectively connected between each output node of the bistable circuit and a pair of data lines. and a non-volatile semiconductor memory element having a drain in, a control electrode at one output node of the bistable circuit, and a floating electrode whose source is connected to the source power supply at the other output node of the bistable circuit, respectively. Characteristic non-volatile random access semiconductor memory. 2. A bistable circuit having a pair of output nodes, first and second switch means connected respectively between each output node of the bistable circuit and a pair of data lines, and a write selection. first and second write selection means that are turned on and off by a signal, and a control electrode that connects the second write selection means to one output node of the bistable circuit through the drain of the first write selection means. a non-volatile semiconductor memory element having a floating electrode whose source is connected to the source electrode at the other output node of the bistable circuit via the non-volatile semiconductor memory element, and between the drain and control electrode of the non-volatile semiconductor memory element and a write power supply; the first, each connected to
A non-volatile random access semiconductor memory comprising a second capacity. 3. The first write selection means is a first insulated gate field effect whose drain is connected to one output point of the bistable circuit, whose source is connected to the drain of the nonvolatile semiconductor memory element, and whose gate is connected to a write selection signal. The second write selection means consists of a transistor,
Claim 2 comprising a second insulated gate field effect transistor having a drain connected to the other output node of the bistable circuit, a source connected to the gate of the nonvolatile semiconductor memory element, and a gate connected to the write selection signal. Non-volatile random access semiconductor memory as described in . 4 A power supply for writing is formed within the same chip,
3. The nonvolatile random access semiconductor memory according to claim 2, comprising a booster circuit that outputs a predetermined write voltage from a single 5V input power source.