JPH03182975A - System for controlling reading of picture memory - Google Patents

Abstract

PURPOSE:To speed up read access by sequentially switching address areas for respective kinds of source data and reading accessing the areas whenever the access sequence of memory banks makes one round, sequentially storing data in a register file and collectively reading them. CONSTITUTION:As to one kind of source data of the continuous address picture elements in respective banks of a picture memory 1, the access sequences of respective banks are executed and the access sequences of respective banks are executed as to other source data. Then, source data are successively accessed with the picture elements of continuous addresses for the number of the banks as a unit. Respective pieces of source data which are read are stored in the register file 2 and the picture elements are sequentially outputted from one where source data are assembled. Thus, high speed access where the merit of bank constitution is made the best use of is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an image memory readout control method for an image processing device, particularly a color image processing device.

The purpose of this study is to enable high-speed access by taking advantage of the bank bottom in a plain pixel type image memory that has a bank bottom.

A register file with a capacity that can store at least each source data of the same number of pixels as the number of memory banks of the image memory is provided, and the address of each source data is accessed by the memory bank in units of consecutive pixels equal to the number of memory banks. Each time the sequence goes around, the address area for each type of source data is sequentially switched, read access to the image memory is performed, and the source data of the read pixels are sequentially stored in the register file and read from one image memory. The configuration is such that for each pixel for which all source data has been read out, the source data is collectively read out from the register file and output.

(Industrial Application Field) The present invention relates to an image memory read control method for an image processing apparatus, particularly a color image processing apparatus.

In recent years, with the advancement of computers, computers that can handle color images have appeared.

Since a color image has three times the amount of information compared to a black and white image, the storage capacity of the image memory that stores the data also has to be reduced.
It is correspondingly huge. In order to display a color image with three times the amount of information on an ice play, an operating speed three times that of a black and white image is naturally required. What is the speed of this operation?

It is greatly affected by the amount of processing time required to access the image memory. The present invention provides means for speeding up read access among the image memory accesses.

[Conventional technology]

Conventional color image memory control circuits use a bus width three times that of monochrome image memory control circuits to increase data transfer. As a result, data transfer speeds for black-and-white and color displays are theoretically the same. In addition, in order to enable high-speed data readout using low-speed memory, we take advantage of rectangular processing, which is a feature of 2-image processing.
An interleaving method using address division has also been used to speed up the reading of data from consecutive pixels that are processed simultaneously.

FIG. 4 shows the basic configuration of a two-image memory.

Pixel data is generally called a pixel, and in the case of a color image, includes R, G, and B color information.

For example, each color information of R, G, and B is represented by 8-bit data.

Pixel storage methods include the packed pixel method, which stores R, G, and B color information three-dimensionally at the same address in the image memory, as shown in FIG.
As shown in b), there is a plain pixel method in which R, G, and B color information is stored two-dimensionally in different address areas of an image memory.

A packed pixel type image memory can read out all the color information of one pixel in one access, and can increase speed because access control is simple. Furthermore, since it is easy to add an error correction code ECC, it is often used when processing speed is important, such as when storing TV image information.

On the other hand, plain pixel image memory.

In order to read out all the data for each pixel, it takes a few (3
access is required, and the addition of ECC is also required for R, G, B
This is not efficient because it is performed for each color information. However, since the R, G, and B color information of an image can be extracted separately, it is often used when it is desired to arbitrarily process the colors of a single image.

FIG. 5 shows a conceptually simplified configuration of a conventional device of the plain pixel type. In the figure, 10 is an incremented 4-puncture image memory, 11 is a data read register for one pixel including four registers that can store four source data, and 12 is an X address (pixel address in the rask). X address counter that generates 1
3 is a source counter that generates a source address for selecting an address area in which source data for color information R, G, and B is stored; 14 is a Y address counter that generates a Y address (rusk address); 15 is a Y address counter that generates a Y address (rusk address); 16 is a source register that gives a recent value to the source counter 13; 17 is a Y start register that gives a preset value to the Y address counter 14; 18 is a
This is an AND circuit that controls the CB (chip enable) terminal of the address counter by matching the strobe pulse for bank driving with the carry of the source counter 13.

At the start of operation, preset values are set in the X start register 15, source register 16, and Y start register 17 by the CPU, and then the precent signal is sent to the X address counter 12. Source counter 13. The signal is applied to each PS terminal of the Y address counter 14, preset is performed, and operation is started.

When the source counter 13 counts strobes equal to the number of source data of R6G, , B, it sends a carry to the AND circuit 18 and causes the X address counter 12 to count +1.

When the X address counter 12 generates addresses for all pixels in the rask, it sends a carry to the Y address counter 14 to increment the Y address by +1.

In this way, banks 0 to 3 of the 9-image memory 10 are sequentially strobed, and in each bank, a source address is generated three times for the X address of one pixel, with the X address being the lower address and the source address being the upper address. Each address area in which R and CB source data are stored is sequentially accessed by three different addresses in the bank, and as a result, R, G, and B data (hereinafter referred to as source data) are read out and the data is read out. It is stored in register 11. When the R, G, and B source data are available in the data read register, they are collectively output to the bus in parallel.

6 and 7 show time charts of image memory access in conventional examples of the conventional packed pixel method and the plain pixel method.

In the packed pixel method time chart shown in Figure 6,
An address and a bank address are generated sequentially every machine cycle, such that bank 0 . 12.3 distributed,
Packed pixel read data (D o
, D +, D 2. ) are sequentially output. In other words, the time chart of the plain pixel method shown in Fig. 7, in which only high-speed readout is performed, corresponds to the conventional device shown in Fig. 5, and the address of 2 pixels is 4.
It is changed once per machine cycle. 1 punk again 3
Three R, G, and B addresses for one pixel are sequentially generated in the strobe. This is because other addresses in the same bank cannot be accessed during each address period (memory cycle).

Therefore, 12 machine cycles are spent on data access for one pixel. For example, source data Ro
, G o, and B o are read out in successive memory cycles of bank 0, stored in the corresponding register portions of the data read register 11 in FIG. 5, and output as Do in the form of a hash.

(Problem to be solved by the invention) In the conventional plain pixel method, even if one image memory has an interleaved configuration by dividing addresses into banks, the function cannot be utilized, and the access speed is lower than in the conventional packed pixel method. The problem was that it was significantly reduced.

An object of the present invention is to enable high-speed access by taking advantage of the advantages of the bank structure in a plain pixel type image memory having a bank structure.

[Means to solve the problem]

The present invention improves the image memory of a plain pixel type image memory having a bank configuration, in which each source data for one pixel is sequentially accessed in the same bank and then accessed for pixels in the next bank. The access sequence of each bank is executed for one type of source data of continuous address pixels of the bank, and then the access sequence of each bank is executed for the other source data, so that □ pixels of continuous addresses as many as the number of banks are executed. Source data is sequentially accessed in units, all read source data is stored in a register file, and the pixels for which source data is complete are sequentially output.

FIG. 1 is an illustration illustrating the principles of the invention in an exemplary manner.

In FIG. 1(a), reference numeral 1 denotes an image memory with a 4-bank configuration, banks O to 3, and each bank has R, G, and G.
, B are provided separately.

2 is a register capacity that can store each source data of the same number of pixels as the number of banks of image memory 1 (in this case, 4×3
) is a register file.

3 is a data read register capable of storing y-space data of one pixel.

FIG. 1(b) shows an access control method in the configuration of FIG. 1(a).

First, for the R area of each bank of one image memory 1, R8,
Access the source data of R1, R2, and R3.

Next, about the G area. ,C,,,G2. Access the source data of G3, and then access B0. B +
, B zB, is accessed.

In the register file 2, these source data of Ro to B3 are read from each bank and are sequentially stored in the register file 2 as shown in the figure.

Data D of the first pixel in which the three source data sets of Ro, Go, and Bo are complete. is read out from the register file 2 to the data read register 3 and output to the bus, and then the pixel data DI+ where the source data is complete
D2. D3 is output one after another.

After outputting D3, the register file 2 becomes empty, and the sequence of accessing the primary source data of R1 to R, , 04 to G7, and 84 to B7 is executed in the same way, and D4 is output.
．． DS, D6. D7 power is applied. The same procedure is performed thereafter.

[Function] According to the present invention, each bank constituting the two-image memory is sequentially accessed every memory cycle, so that the source data of pixels can be sequentially read out at the access speed inherent to the bank-configured image memory. However, for one pixel, each source data is read out every round of the bank access sequence, so waiting time is required.
If the average readout speed is taken for all the pixels of the number of banks (four in this case), it is possible to significantly improve the readout control method compared to the conventional brain pixel method.

[Embodiment] FIG. 2 shows a partly conceptually simplified configuration of an apparatus according to an embodiment of the present invention.

In FIG. 2, 10 is an image memory, 11 is a pig read register, 12 is an X address counter, 13 is a source counter 114 is a Y address counter, 15 is an X start register, 16 is a source register, 17 is a Y start register, 1821.22. 23 is an AND circuit, 19 is a register file, and 20 is a quaternary counter.

Note that the same reference numerals are given to the same elements as those in the conventional device shown in FIG. 5, and the description of the operating functions in FIG. Here, duplicate explanations will be omitted.

The register file 19 stores R for each of the four pixels.
It has a 4×4 register capacity that can store four pieces of source data including source data of , G, and B.

The quaternary counter 20 counts each access to banks 0 to 3, and when the access sequence consisting of four accesses is completed, it sends a carry to the AND circuits 18 and 21, and the CE terminals of the X address counter 12 and source counter 13 are Turn it on and make each counter count +1.

In other words, each time a bank access completes, the source counter 13 is incremented by 1, the upper address is updated, and the access area of the image memory 10 is switched to the next source data area (
For example, from the R area in FIG. 1(a) to the G area, and then
from area to area B).

When the source counter 13 counts the number of source data (3) required for each pixel, the source counter 13 outputs a carry to the AND circuit 1.
8, and the AND circuit 18 increments the X address counter 12 by +1 when the 3-man power is ON. As a result, the X address is increased by 1 in each bank (for example, the first
In (a) of the figure, from R8 to R6).

In the register file 19, the register position in which data is written is controlled according to the bank access of the two image memories IO and the area type of source data RG and B accessed. Then, when the R, CB source data of each pixel is ready, a set of the source data R, G, B is read out and set in the 1 data readout register 11. The R, G, B data set in the data read register 11 is then sent to the bus.

FIG. 3 is a time chart 1 for explaining the operation of the apparatus of the first embodiment shown in FIG.

As shown in the figure, each address (X
The access sequence for banks O to 3 is executed for each address), the read result source data is written to the register file 19, and each time the value of the quaternary counter 20 and the X address counter 12 becomes 0, the register file 19 Karari. ~D3 is read.

5 [Effects of the Invention] According to the present invention, the readout speed of the readout control using the conventional plain vixel method can be almost multiplied by the number of banks, and the performance of one image processing device can be greatly improved.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the apparatus of the invention, Fig. 3 is a time chart 1- of the apparatus of the embodiment of the invention, and Fig. 4 is an image memory Configuration explanatory diagram, 5th
FIG. 6 is a time chart of a conventional example using the punctured pixel method. FIG. 7 is a time chart of a conventional example using the plain pixel method. 1 in Figure 1: Image memory 2; Register file 3: Data read register

Claims (1)

[Claims] The address of a pixel in the image space takes a one-dimensional address format, and the address is divided into a plurality of memory banks determined by a predetermined number of lower bits in an interleaved format,
Further, each of the pixels is composed of a plurality of different types of source data, and each source data of one pixel is stored in a separate address area determined for each type within the same memory bank. In the processing device, a register file having a capacity that can store at least each source data of the same number of pixels as the number of memory banks of the image memory is provided, and the address of each source data is set in units of consecutive pixels as many as the number of memory banks. , the memory bank access sequence is generated so as to sequentially switch the address area for each type of source data every time the memory bank access sequence completes one cycle, perform read access to the image memory, and sequentially store the source data of the read pixels in the register file. An image memory read control method characterized in that, for each pixel for which all source data has been read out from the image memory, the source data is collectively read out from a register file and output.