JPH03182978A - Pattern collation method - Google Patents

Abstract

PURPOSE:To exclude a large quantity of pseudo faults which occur in an edge part by giving a limited edge width to the edge of a reference pattern so as to generate an edge area and setting the pseudo fault part of an observation pattern area corresponding to the edge area to be an area beyond the object of comparison/collation. CONSTITUTION:The limited edge width is given to the edge of the reference pattern consisting of the area of a value '0' and the area of a value '1' and the edge area 3 is generated. The pattern of the edge area 3 is set to be an auxiliary reference pattern, an input pattern is compared and collated to the reference pattern and a compared result pattern showing a difference between the patterns is compared with the auxiliary reference pattern. A coincident part is judged to be a collation indefinite area. Thus, the pseudo fault of the edge part is excluded while an isolated pattern fault, a pattern cut, the short of the pattern and the lack of the pattern can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern matching method that compares and matches a binary or multivalued pattern such as an LSI pattern or a printed pattern with a reference pattern to extract differences between the patterns.

[Prior art]

Defects included in the pattern can be detected by reading the LSI pattern or printed pattern with a microscope or the like to obtain a pattern image, and comparing and collating the pattern image with an image of a reference pattern. In this case, the reference pattern can be obtained from a raw observation pattern with extremely high accuracy in terms of position and density, or it can be obtained from design data. Since the observed pattern image contains noise and magnification errors, when comparing it with the reference pattern image, false defects will be detected even if the pattern is ideally created.

In addition, when the reference pattern image is a binary image, the pattern image is binarized and compared and matched, but due to the setting of the binarization threshold, the edges of the pattern cannot be obtained correctly, resulting in false defects. . Therefore, in the past, defect images obtained through comparison and verification were enlarged/reduced or reduced/enlarged to eliminate elongated false defects at edges and small isolated points due to noise, that is, false isolated defects.

An example of this is shown in FIG. The solid line A is the outline of the observed pattern image of the LSI wafer, and the broken line B is the outline of the designed pattern. A diagonal line C indicates a portion where a difference is detected after comparison.

[Problem to be solved by the invention]

By the way, as mentioned above, the position of the pattern boundary part, that is, the edge part, is uncertain due to image noise, 1 resolution, magnification error, and in some cases, pattern position shift, so it is detected in large quantities similar to the edge density. The shaded areas are often treated as false defects and should be eliminated. Therefore, in order to eliminate these false defects, scaling and scaling are performed. As a result, the shaded area c1. C7, C4, C6, C7 disappear,
C3 and C5 are distinguished as defects. However, the defects that should originally be identified are:
, C6, C7, and in the above method, C7, C4°C6 and C7 are not identified.

In particular, CG and C7 are serious defects in LSI patterns, but the fact that they are not identified is a sacrifice made by eliminating false defects in edge regions that occur in large numbers, and is a serious problem. Therefore, it has not been possible to eliminate false defects at edges and not overlook small serious defects.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a pattern matching method that can detect isolated pattern defects, pattern breaks, pattern short circuits, pattern omissions, etc. while eliminating false defects at edges. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a pattern matching method for comparing and matching an input pattern and a reference pattern, in which a finite edge width is given to the edge of the reference pattern to create an edge area, and the edge area is The pattern is set as a sub-reference pattern, a comparison is made between the input pattern and the reference pattern, a comparison result pattern indicating a difference between the patterns is obtained, and the comparison result pattern and the above-mentioned sub-reference pattern are compared and matching portions are obtained. The most important feature is to determine that the area is a verification uncertainty region.

Further, an edge area is created by giving a finite edge width to the edge of the reference pattern, the pattern of the edge area is used as a sub-base car pattern, and the code of each pixel of the sub-reference pattern and the reference pattern is used as a logical threat. A synthetic reference pattern is created that combines the codes of both patterns, and the synthetic reference pattern and the input pattern are compared to extract matched parts, mismatched parts, and uncertain matching parts of the patterns. do.

[Effect]

According to the above-mentioned means, an edge region is created by giving a finite edge width to the edges of a reference pattern, the pattern of the edge region is used as a sub-reference pattern, and a comparison is performed between the input pattern and the reference pattern; Either a comparison result pattern indicating a difference between the patterns is obtained, the comparison result pattern is compared with the sub-reference pattern, and the matching portion is determined to be a matching uncertain region, or the pattern in the edge region is sub-referenced. a synthetic reference pattern which is a reference pattern and combines the codes of both patterns by logically interpolating the code of each pixel of the sub-reference pattern and the reference pattern;
The synthesis reference pattern is compared with the input pattern to extract matched parts, mismatched parts, and uncertain matching parts, so that isolated pattern defects can be eliminated while eliminating false defects at edges. , pattern breakage, pattern short circuit, pattern omission within a pattern, etc. can be detected.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example 1] Figures 1A and 1B are diagrams for explaining Example 1 of the pattern matching method of the present invention, and Figure 1A is a diagram showing the reference pattern of Example 1. So, the value is 110″′
and the area of value ``1''.The dashed line is the value II
It shows the O++ region and the value LL I I+ region region boundary, and is the same as the broken line in FIG.

FIG. 1B shows a sub-reference pattern in which widths are added to both sides of the pattern boundary of the first embodiment, which are used as edge regions, and a value of "3'" is assigned.

FIG. 2 is a block diagram showing a schematic configuration of an apparatus for carrying out the pattern matching method of the first embodiment.

In FIG. 2, 1 is a data input device, for example,
Use a keyboard, mouse, etc. A pattern input device 2 converts a pattern on an LSI wafer into an optical image using, for example, a scanning microscope, scans it, and inputs it as image data. 3 is a processing device consisting of a computer. 4 is an output device, and the processing device 3
Output the processed results. A program memory 5 stores a control program for controlling the processing device 3. Reference numeral 6 denotes a processing memory that stores images on which processing operations and the like are performed. 7 is an external memory for storing images and data, such as a magnetic disk, an optical disk,
Use magnetic tape, etc.

Next, the processing procedure of the pattern matching method of this embodiment will be explained.

FIG. 3 is a flowchart showing the processing procedure of the pattern matching method of the first embodiment.

The processing procedure of the pattern matching method of this embodiment is as shown in Fig. 8-3, in which an image of an observed pattern is input using the pattern input device 2 shown in Fig. 2 (step 101).
. The processing device 3 calculates a binarization threshold value for the image of the observation pattern (step 102), and binarizes the image of the observation pattern (to "0" or "1") using this binarization threshold value (step 103). This binarized image data of the observation pattern is temporarily stored in the processing memory 6.

On the other hand, the reference pattern (Fig. 1A) is input into pattern input bag M2.
The edge of this reference pattern is detected by the processing device 3 (step ↓05).
. An edge width area is created for this detected edge (step 106), and a value "3" is assigned to this edge width area to create a sub-reference pattern (a reference pattern modified by adding "3" to "O++111"). (step 107
), are temporarily stored in the processing memory 6.

Next, the binarized image data of the observed pattern and the sub-reference pattern values are read out from the processing memory 6, and the difference between them is calculated (step 108).

This difference value is classified (defect extraction) (step 109);
A file is output (step 110) and displayed on the output device 4 (step 111).

Figure 4 shows the binary observation pattern in Figure 7 with the value “01”.
7,111+1, subtracted from the sub-reference pattern of FIG. 1B.

For the value "0" or II II II in the sub-reference pattern, the subtraction value is 1" or "O" or rr 1", the value "1" is an excess pattern or short circuit, and the value "l" is a pattern A cutout or pattern cutout, the value II O++ represents a match.

On the other hand, for the sub-reference pattern value II 3 ++, the value -
2" or "-3". Therefore, areas where the subtraction value is less than -1 can be excluded from comparison or matching areas. At this time, C2, C3, C4, Cs in FIG.
, Cs, C7, the subtraction value is LL I ++111"
111+1 1”-1”I ++,
Excessive patterns, pattern omissions, pattern short circuits, and pattern breaks can be clearly detected.

Note that if defects larger than a desired size are to be extracted, reduction/enlargement and enlargement/reduction may be performed at this stage.

[Example 2] The processing procedure of the pattern matching method of the second embodiment will be explained.

FIG. 5 is a flowchart showing the processing procedure of the pattern matching method of the second embodiment.

In the processing procedure of the pattern matching method of the second embodiment, as shown in FIG. 3, an image of an observed pattern is input using the pattern input device 2 shown in FIG. 2 (step 201). The processing device 3 calculates a binarization threshold for the image of this observation pattern (step 202), and binarizes the image of the observation pattern using this binarization threshold (II OII or +i 1 n
) (step 203). The image data of this two-planted observation pattern is temporarily stored in the processing memory 6. Then, the reference pattern (FIG. 1A) is inputted into the pattern input device 2 (step 204), the binarized image data of the observation pattern is read out from the processing memory 6, and the difference between the two is calculated (step 205). .

On the other hand, edges of the J&1<'j pattern (first AI\1) are detected by the processing device 3 (step 206).
.

An edge width area is created for this detected edge, and a side base pattern is obtained by adding '3'' to this edge width area (
Step 207).

Next, the calculated difference is other than II OI+, and
For pixels other than ``'0'' of the side group or pattern value u 3 II and which is ``3'' in the sub-reference pattern, rr
3 Add u (Step 208), output this to a file (Step 209), and output -1" or " to the output device 4.
1” is displayed (step 210).

In other words, in the pattern matching method of Embodiment 2, as shown in FIG. 6, the binary observed pattern consists of ``O''''''1'', and its distribution is as shown in FIG. Assume that it is the same as

When the reference pattern shown in FIG. 1A is subtracted from the binary observation pattern shown in FIG. 7, the shaded area in FIG.
1”, and the others are LL OII.

Next, the pattern in FIG. 7 and the pattern in FIG. 1B are compared by using FIG. 1B representing the edge area of the reference pattern as a sub-reference pattern. In this case, since it is sufficient for the sub-reference pattern to distinguish between an edge area and a non-edge area, the edge area may be "D" and the others may be "O". In the case of numbering as shown in Figure 1B, converting the shaded part in Figure 7 in the area "3" in Figures 1A and 1B to LL 3 II results in Figure 6, which is II I T+ or 111+1. If identified, false defects C□ will be eliminated, and C21c3. c.
,,c,.

C,,C,can be clearly identified.

As can be seen from the above description, according to the embodiment 1-2, the edge region II 3 II is created by giving a finite edge width to the edge of the reference pattern, and the edge region +13
By setting the false defect part of the observed pattern area corresponding to 1+ as the area not subject to comparison or matching, or the forced matching area, excessive patterns, missing patterns, short circuits, and broken patterns that occur outside the edge area can be preserved while preserving them. A large number of false defects can be eliminated.

In addition, fine small pattern chips and protrusions on the edges,
If the size is smaller than the edge width, it will be rejected, so the present invention is not suitable for detecting this.

However, small protrusions or chips on the edges are generally unimportant and can be ignored in most cases. Therefore, excluding the detection of small protrusions and chips at the edges generally meets the normal inspection conditions.

In addition, in Examples 1 and 2, binary images or binary images obtained by binarization processing were targeted, but since the only condition is that edge regions can be distinguished from others, multivalued images are also targeted. It is clear that this can be done.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, an edge region is created by giving a finite edge width to the edge of a reference pattern, and a false defect portion of an observed pattern region corresponding to the edge region is compared with the non-verification target region. Alternatively, by forming a forced matching area, it is possible to eliminate a large number of false defects occurring at the edge portions while preserving excessive patterns, missing patterns, short circuits, and broken patterns outside the edge portions.

[Brief explanation of drawings]

1A and 1B are diagrams for explaining a first embodiment of the pattern matching method of the present invention, and FIG. 2 shows a schematic configuration of an apparatus for implementing the pattern matching method of the first embodiment. 3 is a flowchart showing the processing procedure of the pattern matching method of the first embodiment; FIG. 4 is a diagram showing the results of comparison between the observed pattern and the sub-reference pattern; FIG. FIG. 5 is a flowchart showing the processing procedure of the pattern matching method of the second embodiment, FIG. 6 is a diagram for explaining the second embodiment of the pattern matching method of the present invention, and FIG. 7 is a diagram showing the conventional pattern matching method. FIG. 3 is a diagram for explaining problems with the matching method. In the figure, 1...data input device, 2. pattern input device,
3... Processing device, 4... Output device, 5... Program memory 6... Processing memory, 7... External memory.

Claims (2)

[Claims] (1) In a pattern matching method that compares and matches an input pattern and a reference pattern, an edge region is created by adding a finite edge width to the edge of the reference pattern, and the pattern in the edge region is used as a sub-reference pattern, and the input pattern and Comparing and matching the reference patterns, obtaining a comparison result pattern indicating a difference between the patterns, comparing the comparison result pattern with the sub-reference pattern, and determining a matching portion as a matching uncertain region. A pattern matching method characterized by: (2) In a pattern matching method that compares and matches an input pattern and a reference pattern, an edge area is created by adding a finite edge width to the edge of the reference pattern, the pattern in the edge area is used as a sub-reference pattern, and the sub-reference pattern is A synthetic reference pattern is created by logically synthesizing the code of each pixel of the pattern and the reference pattern, and combines the codes of both patterns.The synthetic reference pattern and the input pattern are compared to determine whether the patterns match or do not match. A pattern matching method characterized by extracting a part and a part whose matching is uncertain.