JPH03183095A - Ram refresh system for microprocessor system - Google Patents

Abstract

PURPOSE:To save labor for exchanging a DRAM, which requires refresh, to an SRAM by generating a refresh signal based on a clock signal when stopping a microprocessor, and refreshing a RAM. CONSTITUTION:When a CPU is operated and an ALE signal is periodically outputted, a counter circuit 10 and an FF circuit 11 are reset each time the signal is outputted. When the CPU is stopped, the ALE signal is not generated even when a clock period from the preceding ALE signal is made 13rd period. The circuit 10 counting this 13rd period regards such a state as debugging time and generates an output at H. The FF 11 is inverted to be H and during the inversion, a refresh signal caused by the clock signal is passed through an AND circuit 13 and outputted from an OR circuit 16. Then, the refresh signal caused by the ALE signal is cut by an AND circuit 15. A comparator circuit 12 compares the count value of the circuit 10 with the ALE signal and when refresh is not executed by the clock signal, the refresh signal is switched.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a refresh method for pseudo-static RAM or dynamic RAM in a device using a microprocessor, and particularly relates to a method for refreshing RAM even when the microprocessor is stopped. The present invention relates to a RAM refresh method for a microprocessor system that enables

[Prior Art] Generally, a microprocessor has a memory element that requires refreshing for memory retention, such as a pseudo-static RAM or a dynamic RAM, or a static RAM, etc., in order to store processed results. Memory elements that do not require refreshing are also used in parallel. The former storage element is normally refreshed based on a bus control output signal (hereinafter referred to as an ALE signal) that is periodically output from the microprocessor while it is operating.

By the way, when developing a program for a microprocessor, it is necessary to use the Depack device as a microprocessor during boat fishing to operate it continuously and stop it, and at that time erase the information stored in the RAM. It is necessary to read it without any errors. And when the microprocessor is stopped, the microprocessor's ALE
Since the signal is not output, the RAM cannot be refreshed using the ALE signal. Therefore, RAM that requires refreshing is replaced in advance with static RAM that does not require refreshing to prevent information in the RAM from disappearing. [Problems to be Solved by the Invention] However, in the method of replacing the RAM with a static RAM as described above, there is a problem in that the static RAM used for this must be prepared separately, which increases the cost.

Further, wiring of the static RAM requires modification such as pattern cutting of the board, which not only takes time but also poses a problem that it is impossible to return to the original state later.

The present invention has focused on the above-mentioned problems and has been devised to effectively solve them.

An object of the present invention is to generate a refresh signal based on a clock signal when the microprocessor is stopped, thereby eliminating the need for replacement with static RAM and improving design evaluation and depacking efficiency. The purpose is to develop a RAM refresh method for microprocessor systems.

[Means for Solving the Problems] The present invention has a RAM that requires a refresh operation to continue retaining data, and the refresh of the RAM is controlled by a bus control output signal of a microprocessor. In a microprocessor system, a continuity detection circuit for detecting continuity of the bus control output signal, an external signal synchronous refresh signal generation circuit for generating a refresh signal in synchronization with the bus control output signal, and a clock signal. When the self-refresh signal generation circuit that generates a refresh signal and the detection circuit detect the continuity of the bus control output signal, the RAM is refreshed with a refresh signal synchronized with this bus control output signal, and On the other hand, a refresh signal switching circuit is provided so that when discontinuity is detected, the RAM is refreshed using the output signal of the self-refresh signal generating circuit.

[Function] During normal operation, since the microprocessor is operating, the ALE signal is output periodically, and the information in the RAM is refreshed by the refresh signal generated based on this ALE signal. Ru.

On the other hand, when performing design evaluation or depacking of a microprocessor program, the operation of the microprocessor is stopped. Then, the output of the ALE signal is also stopped. At this time, the continuity detection circuit immediately detects the stoppage of the output of the ALE signal and switches the refresh signal switching circuit so that the RAM is refreshed with the refresh signal generated based on the clock signal.

As a result, the refresh signal is not interrupted, and even if a RAM that requires a refresh operation is used, information such as received data stored in the RAM is retained without being lost.

[Embodiment] A preferred embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 4 is a schematic diagram showing a microprocessor system for using the RAM reflex nosh method according to the present invention.

Here, the microprocessor 1 controls, for example, a dot matrix printer (not shown), and a read only memory (ROM) 2 stores programs necessary for printing and font data such as characters and symbols. A random access memory (RAM) 3 temporarily stores data received from the outside.
A refresh operation is required to retain these received data. The I10 driver 4 receives instructions from the microprocessor 1 and drives the input/output device.

The above microprocessor 1. ROM2, RAM3 and I
The 10 drivers 4 are connected to each other by path lines 5, so that data and commands can be sent and received.

The r10 driver 4 includes an interface circuit for interfacing with an external device (not shown);
A print head for printing, a line feed motor for line feed, and a spacing motor for moving the print head in the printing direction are connected.

The printing operation of the dot matrix printer is performed as follows. First, when a character code is received from a system such as a personal computer, font data is extracted from the storage address of the ROM 2 corresponding to this code, and the print head is driven as dot drive information for the print head to perform printing.

In addition, data received from systems such as personal computers and dot drive information for printing are temporarily stored in RAM, but this RAM must be refreshed periodically to maintain the stored state. .

The RAM refresh method according to the present invention will be adopted in the system configured as described above.

FIG. 1 shows RAM! according to the present invention. FIG. 2 shows a schematic block diagram of an example J-Fresh method.

As shown in the figure, the external signal synchronized refresh signal generation circuit 6 receives the R
The self-refresh signal generation circuit 7 is a circuit that generates an AM refresh signal, and the self-refresh signal generation circuit 7 is a circuit that generates a RAM refresh signal based on a clock signal of an oscillator (not shown). Both circuits 6 and 7 are connected to a refresh signal switching circuit 8 for switching these refresh signals.

Further, the ALE signal is also manually inputted to a continuity detection circuit 9 for detecting whether or not this signal is continuously output. This continuity detection circuit 9 is connected to the refresh signal switching circuit 8, and outputs the detection result to this switching circuit 8. Here, the switching circuit 8 detects that the detection signal from the continuity detection circuit 9 is AL.
When the E signal indicates continuity, the refresh signal from the external signal synchronized refresh signal generation circuit 6 is output; on the other hand, when the detection signal indicates that the ALE signal is not continuous and has been interrupted, It is configured to output a refresh signal from the self-refresh signal generation circuit 7.

Here, the external signal synchronized refresh signal generation circuit 6
With the ALE signal as input, the refresh signal necessary for the RAM can be generated by combining several stages of flip-flop circuits, and the self-refresh signal generation circuit 7 can generate the refresh signal generation circuit synchronized with the external signal. Similarly to 6, it can be constructed by combining several stages of flip-flop circuits.

The continuity detection circuit 9 and the refresh signal switching circuit 8 are specifically constructed as shown in FIG.

FIG. 2 is a diagram showing the configuration of the continuity detection circuit 9 and refresh signal switching circuit 8.

As shown in the figure, the continuity detection circuit 9 includes a counter circuit 10 that counts clock signals, and a counter circuit 10 that counts clock signals.
It is mainly composed of a flip-flop circuit 11 which receives an input when the count number reaches a predetermined number, for example 13, and a comparison circuit 12 which compares the output of the counter circuit 10 and the ALE signal. The outputs from the comparison circuit 12 are connected to the reset inputs of the counter circuit 10 and flip-flop circuit II, respectively.

The flip-flop circuit 11 has an L level when the ALE signal is input, that is, when the ALE signal is continuous.
ow", and conversely, when the counter circuit 10 is manually operated, that is, when the ALE signal is not continuous but interrupted, it is set to "High", and based on this, the refresh signal is switched as described later. It will be done.

On the other hand, the refresh signal switching circuit 8 includes a first AND circuit 13 that manually inputs the output of the flip-flop circuit 11 and a refresh signal generated by a clock signal, and a first AND circuit 13 that inputs the output of the flip-flop circuit 11 and a refresh signal generated by the clock signal;
4 and the refresh signal generated by the ALE signal.
It is mainly composed of an AND circuit 15 and an OR circuit 16 which outputs a refresh signal using the outputs from the first and second AND circuits 13 and 15 as a human input.

Next, the operation of the circuit configured as described above will be explained.

First, the CPU clock signal and ALE used here
An example of the relationship with signals will be explained based on FIG.

One machine cycle is made up of 6 periods of a clock signal, and long instructions such as reading and writing from RAM are made up of 12 periods of a 2-man cycle clock signal. The ALE signal is not generated in the second half of the two machine cycles of the long instruction. Also,
During CPU operation, instructions (RD/WR in the illustrated example)
) are never uttered consecutively. Therefore, during normal operation of the CPU, after the previous ALE signal is output from the CPU, the next A, LE signals will be output if the clock signal has a period of 13 cycles at most.

However, during design evaluation or depacking, it is possible to stop the depacking machine after executing the command, so no ALE signal is generated even if the clock signal has a period of 13 cycles.

Under such circumstances, the operation of the circuit shown in FIG. 2 will be explained.

As mentioned above, during normal operation of the CPU, the AL
The E signal is output continuously, ie, once every one machine cycle or every two machine cycles. This ALE signal is inputted to the reset terminal of the flip-flop circuit 11 via the comparison circuit 12, and is periodically reset. As will be described later, there is no "High" input from the counter circuit 10 between two consecutive reset signals, and therefore, the flip-flop circuit 11 receives the reset signal that is periodically input during normal operation of the CPU. (A
LE signal) is always set to "Low".

The output from this flip-flop circuit 11 is branched into two, one of which is input to a first AND circuit 13, where it is ANDed with a refresh signal based on a clock signal. Here, since the output from the flip-flop circuit 11 is maintained at "Low" as described above, the output from the first AND circuit 13 also becomes "Low", and as a result, the refresh signal based on the clock signal is transmitted to the OR circuit 16. It is never output from.

On the other hand, the other branched output is output from the inverter 1.
4 and becomes High'', and this signal is inverted by the second
The signal is input to the AND circuit 15, where it is ANDed with the refresh signal based on the ALE signal. This refresh signal is then outputted from the OR circuit 16 via the second AND circuit 15.

Therefore, during normal operation of the CPU, a refresh signal based on the ALE signal is output to the RAM.

Next, when performing design evaluation or depacking, as a result of stopping the CPU midway, the output of the ALE signal will be stopped midway, and the operation at this time will be described.

First, when the CPU is operating and the ALE signal is output periodically, the counter circuit 1
0 and the flip-flop circuit 11 were reset, but when the operation of the CPU is stopped, no ALE signal is generated even if the clock cycle changes to 13 cycles from the previous generation of the ALE signal.

Then, this 13 cycle type counting circuit l
O assumes that it is depacking time and outputs the output from now as “
High.Then, the next stage flip-flop circuit 11 is inverted and set to High.
In the state of ``high'', the next AL after depacking etc. is completed.
It will be held until the E signal is input. and,
While the output of the flip-flop circuit 11 is 'High', a refresh signal based on the clock signal is output from the OR circuit 16 via the first AND circuit 13, contrary to the above, and the refresh signal based on the ALE signal is output from the OR circuit 16 via the first AND circuit 13. The signal will be cut by the second AND circuit 15.

In this way, during normal CPU operation, the ALE signal is generated continuously, so the ALE signal is used to generate the refresh signal.On the other hand, when the ALE signal is not generated continuously, such as during design evaluation or depacking, In this case, it is possible to switch to a refresh signal based on an oscillator clock signal.

By the way, when the RAM is refreshed by a refresh signal based on a clock signal, if the refresh signal is switched immediately when the ALE signal is input, if refresh is being performed at that time, it will not be refreshed normally. Therefore, in order to eliminate such problems, we need a comparison circuit! At step 2, both the count value of the counter circuit 10 and the ALE signal are compared, and the refresh signal is switched when refresh is not performed by the clock signal.

As described above, according to this embodiment, the refresh signal is always generated, so that when debugging a system that controls a dot matrix printer,
Even if the microprocessor is stopped, the RAM that stores received data and dot drive information for printing can be refreshed. Therefore, the RAM that requires refreshing during debugging can be refreshed. Even if you do not replace the static RAM with an unnecessary static RAM in advance, the information in the RAM will not disappear.

Also, since there is no need to replace static RAM,
There is no need to modify the board for static RAM wiring, such as cutting a pattern, or to restore it.

Incidentally, in the explanation of the above embodiment, one machine cycle was explained as corresponding to six periods of the clock signal, but it is needless to say that the present invention is not limited to this.

(Effects of the Invention) According to the present invention, by determining the presence or absence of a bus control output signal,
During normal operation, when the bus control output signal is generated continuously, a refresh signal is generated by the bus control output signal to refresh the RAM, and on the other hand, the Depak special bus control output signal is not generated continuously. when,
By creating a refresh signal using a clock signal and using this to refresh the RAM, a refresh signal is always available, so dynamic RAM that requires refreshing during design evaluation and debugging can be
It is possible to save the effort of replacing the RAM with a static RAM that does not require refreshing.

Therefore, design evaluation and device efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of the RAM l) refresh method according to the present invention, FIG. 2 is a block diagram showing an embodiment of a refresh signal switching circuit and a continuity detection circuit, and FIG. FIG. 4 is a timing chart showing the relationship between the clock signal and the ALE signal. FIG. 4 is a schematic diagram of the microprocessor system. 6... External signal synchronized refresh signal circuit, 7...
Self-refresh signal generation circuit, 8... Refresh signal switching circuit, 9... Continuity detection circuit.

Claims (1)

[Scope of Claims] A microprocessor system having a RAM that requires a refresh operation to continue retaining data, and in which the refresh of the RAM is controlled by a bus control output signal of a microprocessor, comprising: a continuity detection circuit for detecting continuity of the control output signal; an external signal synchronized refresh signal generation circuit for generating a refresh signal in synchronization with the bus control output signal; and a self-refresh circuit for generating a refresh signal in accordance with a clock signal. When the signal generation circuit and the continuity detection circuit detect the continuity of the bus control output signal, output the output signal from the external signal synchronous refresh signal generation circuit as a refresh signal for the RAM, and and a refresh signal switching circuit that outputs an output signal from the self-refresh signal generation circuit as a refresh signal for the RAM when the nature detection circuit detects discontinuity in the bus control output signal. RAM refresh method for microprocessor systems.