JPH03183155A - High-frequency and high-output hybrid integrated circuit - Google Patents

High-frequency and high-output hybrid integrated circuit

Info

Publication number
JPH03183155A
JPH03183155A JP1321885A JP32188589A JPH03183155A JP H03183155 A JPH03183155 A JP H03183155A JP 1321885 A JP1321885 A JP 1321885A JP 32188589 A JP32188589 A JP 32188589A JP H03183155 A JPH03183155 A JP H03183155A
Authority
JP
Japan
Prior art keywords
insulating substrate
integrated circuit
hybrid integrated
transistor chip
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1321885A
Other languages
Japanese (ja)
Inventor
Tetsuo Kobayashi
小林 徹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1321885A priority Critical patent/JPH03183155A/en
Publication of JPH03183155A publication Critical patent/JPH03183155A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the height of an integrated circuit, to improve a thermal resistance and to shorten the length of a bonding wire by a method wherein the thickness in a mounting part of a transistor chip on an insulating substrate is made thin. CONSTITUTION:An insulating substrate 2 in a mounting part of a transistor chip 6 is made thinner than in other parts of the insulating substrate 2; as a result, the whole height of a hybrid integrated circuit can be made thin. Alumina or the like is used generally for the insulating substrate 2 because its cost is low; however, its resistance is high. When the insulating substrate 2 in the mounting part of the transistor chip is made thin, a thermal resistance can be improved. An interval between the upper part of the transistor chip 6 and the insulating substrate 2 can be made small; as a result, the length of bonding wires 7 can be made short.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高周波高出力混成集積回路の絶縁基板に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulating substrate for a high frequency, high power hybrid integrated circuit.

〔従来の技術〕[Conventional technology]

第2図は従来の高周波高出力混成集積回路の断面図であ
る。図において、(1)は鋼等の放熱器を兼ねる接地用
金属板、(2)は接地用金属板(1)上に取付けられた
絶縁基板、(3)は絶縁基板(2)上に設けられた表面
導体層、(4)は金属板、(5)はエミッタブリッジ、
(6)はトランジスタチップ、(7)はボンディングワ
イヤである。
FIG. 2 is a cross-sectional view of a conventional high frequency, high power hybrid integrated circuit. In the figure, (1) is a grounding metal plate made of steel that also serves as a radiator, (2) is an insulating board mounted on the grounding metal plate (1), and (3) is an insulating board mounted on the insulating board (2). (4) is a metal plate, (5) is an emitter bridge,
(6) is a transistor chip, and (7) is a bonding wire.

次に動作について説明する。Next, the operation will be explained.

高周波高出力混成集積回路は金線等によるボンディング
ワイヤ(7)により、絶縁基板(2)上に設けられた表
面導体層(3)に接続され、トランジスタとしての機能
を果すこととなる。なか、ここではボンディングワイヤ
(7)の長さを短かくするためエミッタブリッジ(5)
を使用している。
The high-frequency, high-output hybrid integrated circuit is connected to a surface conductor layer (3) provided on an insulating substrate (2) by a bonding wire (7) made of a gold wire or the like, and functions as a transistor. Here, in order to shorten the length of the bonding wire (7), the emitter bridge (5)
are using.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の高周波高出力混成集積回路は以上のように構成さ
れていたので、すべての部品を縦方向に接続しているた
め全体的な高さが高くなってしまい、筐た、トランジス
タ直下の絶縁基板が他の部所と同じ厚さであり、絶縁基
板の熱抵抗は一般的には大きいことから、放熱のための
特別の配慮が必婆となりまた、ボンディングワイヤ長が
相対的に長くなってし會うために、トランジスタのワイ
ヤ長が長くなってし1うといったような問題点があった
Conventional high-frequency, high-output hybrid integrated circuits were constructed as described above, and all components were connected vertically, resulting in an overall high height. The thickness of the bonding wire is the same as that of other parts, and the thermal resistance of the insulating substrate is generally large, so special considerations for heat dissipation are required, and the length of the bonding wire is relatively long. There was a problem in that the length of the transistor wires had to be long to meet each other.

本発明は上記のような問題点を解消するためになされた
もので、混成集積回路の高さを低減するとともに、熱抵
抗の低減、ボンディングワイヤ長を短くし高周波特性の
改善をはかった混成集積回路を得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and is a hybrid integrated circuit that reduces the height of the hybrid integrated circuit, reduces thermal resistance, shortens the bonding wire length, and improves high frequency characteristics. The purpose is to obtain a circuit.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る高周波高出力混成集積回路は、絶縁基板の
トランジスタチップ装着部の厚さを4くすることにより
、集積回路の高さを低減するとともに、熱抵抗の改善、
ボンディングワイヤ長の短縮をはかったものであろう [f$i用J 本発明にかける高周波高出力混成集積回路は、トランジ
スタチップ装着部の絶縁基板を薄くすることにより、回
路の高さが低減されるとともに、熱抵抗が改善され、ま
た、ボンディングワイヤが短かくなるため高周波特性が
改善される。
The high-frequency, high-output hybrid integrated circuit according to the present invention reduces the height of the integrated circuit by reducing the thickness of the transistor chip mounting portion of the insulating substrate to 4, and improves thermal resistance.
The high-frequency, high-output hybrid integrated circuit of the present invention probably aims to shorten the length of the bonding wire. At the same time, thermal resistance is improved, and high frequency characteristics are improved because the bonding wire is shortened.

〔実施例〕 以下1本発明の一実施例を図について説明する。〔Example〕 An embodiment of the present invention will be described below with reference to the drawings.

第1図において、(1)は放熱器を兼ねる接地用金属板
、(2)は接地用金属板(1)上に融着等にて接触され
る絶縁基板で、この絶縁基板(2)は所望の部位が他の
部位よりも薄い厚さで作られている。(3)は絶縁基板
(21上にパターン化され設置される厚膜等による表面
導体層、(4)は表面導体層上に設けられた金属板で、
絶縁基板(2)の薄い部位に放熱効果改善のために設け
られている。(6)はトランジスタチップで、金属板(
4)上にマウントされる。(5)はエミッタワイヤボン
ディング用のエミッタブリッジを示す。
In Figure 1, (1) is a grounding metal plate that also serves as a heatsink, and (2) is an insulating substrate that is connected to the grounding metal plate (1) by fusion bonding or the like. Desired areas are made with a thinner thickness than other areas. (3) is a surface conductor layer such as a thick film patterned and installed on an insulating substrate (21), (4) is a metal plate provided on the surface conductor layer,
It is provided in a thin portion of the insulating substrate (2) to improve the heat dissipation effect. (6) is a transistor chip, and the metal plate (
4) Mounted on top. (5) shows an emitter bridge for emitter wire bonding.

こうしてなる混成集積回路はトランジスタチップ(6)
上の各電極と、表面4体層(3)、もしくはエミッタブ
リッジ(5)等がボンディングワイヤ(7)により接続
される。
The resulting hybrid integrated circuit is a transistor chip (6)
Each of the upper electrodes is connected to the surface four-layer (3) or the emitter bridge (5) or the like by a bonding wire (7).

次に動作を下記に説明する。Next, the operation will be explained below.

1)トランジスタチップ(6)の設置部の絶縁基板(2
)が他部の絶縁基板(2)部位よシ薄くなっているため
1) Insulating substrate (2) for installation part of transistor chip (6)
) is thinner than the other part of the insulating board (2).

混成集積回路の全体の高さを薄くすることができる。The overall height of the hybrid integrated circuit can be reduced.

2)絶縁基板(2)には、その価格が廉価であることか
ら、アルミナ等を一般的には使用するが、この熱抵抗が
高いため、高出力用トランジスタチップ(6)を使用す
る場合、従来は特別な配慮が必要としたが、トランジス
タチップ装着部の絶縁基板(2)が薄くなっているため
、熱抵抗の改善がはかられる。
2) Alumina or the like is generally used for the insulating substrate (2) because it is inexpensive, but because of its high thermal resistance, when using a high-output transistor chip (6), Conventionally, special considerations were required, but since the insulating substrate (2) in the transistor chip mounting area is thinner, thermal resistance can be improved.

3)トランジスタチップ(6)上部と絶縁基板(2)と
の間隔が小さくなすこのため、ボンディングワイヤ(7
)長を短かくすることができる。ボンディングワイヤ(
7)はそれ自体がインダクタとして作用するためツイヤ
長が短かくなればその分インダクタ成分が減り、高周波
特性を向上させることができる口な釦、上記5j!施例
では放熱改善のための金属板(4)を用いた場合につき
示したが、この金属板(4)が無くともよい。
3) Because the distance between the upper part of the transistor chip (6) and the insulating substrate (2) is reduced, the bonding wire (7)
) length can be shortened. Bonding wire (
7) is a button that itself acts as an inductor, so if the wire length is shortened, the inductor component is reduced accordingly, and the high frequency characteristics can be improved. In the embodiment, a case is shown in which a metal plate (4) is used for improving heat radiation, but this metal plate (4) may not be used.

【発明の効果j 以上のように本発明によれば、絶縁基板をうすくしただ
けのものであり、高周波高出力混成集積回路をうずくか
つ高性能にできる効果がある
[Effects of the invention j As described above, according to the present invention, the insulating substrate is simply made thinner, and it has the effect of making a high-frequency, high-output hybrid integrated circuit both effective and high-performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による高周波高出力α或集積
回路を示す断面図、第2図は従来の高周波高出力混成集
積回路を示す断面図である。 図において、(1)は接地用金属板、(2)は絶縁基板
(3)は表面導体層、(4) Fi金属板、(5)はエ
ミッタブリッジ、(6)はトランジスタチップ、(7)
はボンディングワイヤを示す。 なか、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a sectional view showing a high frequency, high power integrated circuit according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional high frequency, high power hybrid integrated circuit. In the figure, (1) is a grounding metal plate, (2) is an insulating substrate, (3) is a surface conductor layer, (4) is an Fi metal plate, (5) is an emitter bridge, (6) is a transistor chip, (7) is
indicates bonding wire. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 高周波高出力混成集積回路において、放熱器を兼ねる金
属導体板の上に設けられる絶縁基板のトランジスタ融着
部分の絶縁基板の厚さを薄くしたことを特徴とする高時
波高出力混成集積回路。
A high-frequency, high-output hybrid integrated circuit characterized in that the thickness of the insulating substrate at the transistor-fused portion of the insulating substrate, which is provided on a metal conductor plate that also serves as a radiator, is made thinner.
JP1321885A 1989-12-12 1989-12-12 High-frequency and high-output hybrid integrated circuit Pending JPH03183155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1321885A JPH03183155A (en) 1989-12-12 1989-12-12 High-frequency and high-output hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1321885A JPH03183155A (en) 1989-12-12 1989-12-12 High-frequency and high-output hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH03183155A true JPH03183155A (en) 1991-08-09

Family

ID=18137491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1321885A Pending JPH03183155A (en) 1989-12-12 1989-12-12 High-frequency and high-output hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH03183155A (en)

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