JPH03183230A - Buffer slip detection circuit - Google Patents

Abstract

PURPOSE:To make the occurrence of buffer slip and the sending of an alarm coincide with each other by delaying the rise-up point of a generative signal to be used for the alarm and the reset of a second pattern generating part later than the rise-up point of a neighboring second pulse to be inputted just after the rise-up point of the pulse synchronized with a line side clock. CONSTITUTION:A control signal generating part 1 sends a write-in control signal to memories 41, 42 by using a first pulse synchronizing with a device side clock, and the control signal generating part 5 sends a read-out control signal to the memories 41, 42 by using the second pulse synchronizing with the line side clock, but when a reset signal is inputted, it holds the read-out control signal at the time of an initial state until the next second pulse is inputted. A phase comparing part 2 outputs the compared result of L level when the phase compared result of the write-in control signal and the read-out control signal becomes within a predetermined access inhibiting zone. At this time, an alarm generating part 6 generates the alarm and the reset signal which have the rise-up points delayed later than the rise-up point of the second pulse neighboring the the compared result of L level by using the line side clock and a second clock.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a buffer slip detection circuit used when outputting data synchronized with a device-side clock in synchronization with a line-side clock, it is possible to always detect the occurrence of a buffer slip and the sending of an alarm. The purpose is to make them match, and the first. The first pulse is synchronized with the second memory and the device clock. The first write control signal is generated by using the full bottom part of the write control signal and the second pulse synchronized with the line side clock to generate the second write control signal. A readout control signal generating section is provided which sends out a second readout control signal, and holds the readout control signal in the initial state when the reset signal is input until the next second pulse is inputted. 1. When writing and reading data to and from the second memory alternately and converting data synchronized with the device clock into data synchronized with the line clock, the write control signal and the read control signal When the comparison result enters a predetermined read access prohibited area, the phase comparison part sends out the comparison result of L level. When the input comparison result is L level, the line side clock and (1) An alarm generation part that generates an alarm and the reset signal, which have a rising point later than the rising point of the second pulse adjacent to the comparison result of the 7 levels, using the second clock; Configure.

[Industrial Field of Application] The present invention relates to a buffer slip detection circuit used when, for example, data synchronized with a device clock is outputted in synchronization with a line clock.

Generally, in order to synchronize data that is synchronized with the device side clock with an asynchronous line side clock, 2For example, two Elastake memories ES are provided, and data is written to these memories using the device side clock.1 Data is written using the line side clock. Read data alternately.

At this time, it is necessary to always make sure that the occurrence of a buffer slip and the sending of an alarm are the same.

[Conventional technology]

FIG. 4 is a diagram showing an example of a clock transfer circuit, FIG. 5 is a circuit configuration diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. Note that the symbols on the left side of FIG. 6 indicate the waveforms of the portions with the same symbols in FIG.

Here, flip-flop II and OR game in FIG.
112 and 13 are constituent parts of #I pattern generation component l.

NAND gate 21. Flip-flop 22. O
The R gate 23 is a component of the phase comparison portion 2, the flip-flop 31, and the OR gates 32 and 33 are components of the #2 pattern raw bottom portion 3. The operation shown in FIG. 5 will be explained below with reference to FIGS. 4 and 6.

First, parallel 8-bit data from the time-division multiplexed bus 43 shown in FIG. 4 is converted into serial data in the parallel/serial conversion section 44, and then transferred to the #I, R2 elastake memory (hereinafter referred to as "#I" and "R2" elasticity memory).

#1. (abbreviated as R2ES) is applied to 41.42.

Next, as shown in FIG. 5, a pulse W8K is input as a clock to a flip-flop (hereinafter abbreviated as FF 01) at 8 synchronized with the device side clock.

This FF is connected to divide the input clock frequency by 2, so the 2 frequency output from this FF is the write inhibit signal -1
It is sent to #IES 41 as 1.

In addition, the OR gate 12 performs an OR with this write inhibit signal and pulse 8, and the write reset signal WRI, which has the same rising point as the write inhibit signal old 1, is sent to the same <#IES 41. (Fig. 6 ■, ■,
■Reference).

It should be noted that the write reset signal WR2, which has the same rising point by misunderstanding half a cycle from the rising point of the write reset signal WRI and the write inhibit signal old 1 (one cycle is defined as the period between the adjacent rising points of the pulse W8), Write inhibit signal WI2
is sent to the R2ES (see Figure 6 - ■, ■).

Here, data can be written to the ES while the write inhibit signals -If and WI2 are at the H level, but
When the level is reached, it becomes impossible to write data to the ES, so as shown in Figure 6-■, ■, the Ill ES,
Writing to the 112 ES is performed alternately every 8 cycles.

Now, the write reset signal -R1 and the write inhibit signal Wll are simultaneously applied to #IES as described above, and writing starts when the former rises.

Since writing is enabled at the rising edge of the latter, data is written to #IES with pulse 5YS64 at device side clock 64. Similarly, 64 for #285.
Data is written to 112ES by pulse 5YS64.

On the other hand, when reading data from Ill ES and #2 ES, similarly to writing, pulse R8K is divided by 2 to 8 synchronized with the line side clock using FF 31 to obtain read inhibit signal R11.

In addition, the OR gate 33 uses the read reset signal RRI obtained by ORing the read inhibit signal R11 and the 8 pulse R8 synchronized with the line side clock and the read inhibit signal RII to start reading and read out. It is read out by the line side clock (not shown) (Fig. 6-■).

[Phase], see ■).

Here, as shown in Figure 6-■ and @, data writing and reading for #IES are adjacent, so if writing and reading collide, data will be damaged.
When a read pulse enters the shaded area (read access prohibited area) shown in Figure 2, the read pulse is shifted by half a cycle to avoid collision.

That is, the write inhibit signal -11 is generated by the NAND gate 21.
is NANDed with the input read access prohibited area signal 5WIND, and when the FF 22 punches out the pulse 5YS64 at 64 synchronized with the device side clock, the L level pulse ^ shown in FIG. 6-2 is obtained.

Then, when this pulse A and the read reset signal RR2 of #2 ES are ORed by the OR gate 23, FIG.
The pulse shown in [phase] is obtained, but with this pulse the FF
When the FF 31 is reset, the terminal Q of the FF 31 becomes in the state, and the read inhibit signal RII, Rr2 maintains the previous state for half a cycle until the next pulse R8K is input (Fig. 6-0). ~@reference).

This causes a buffer slip in which the same data of Ill ES is read twice, so the OR gate 23
Sends the output as an alarm.

Here, the OR gate 23 takes the OR of pulse A and the read reset signal RR2 of #2 ES, but the rising point of this read reset signal can also be set by starting data read from #2 ES as described above. Therefore, before that, III ES is read using the read reset signal RRI, and #IES
Collisions between writing and reading are monitored using the read reset signal RR2.

Also, if there is no conflict between writes and reads.

The read reset signals RRI and RR2 are shown in FIG. 6 - [Phase].

As shown in ■, A, B and C should appear alternately, but by shifting by half a cycle, RRI does not appear in the position of .
Second, the read reset signal RR2 appears twice, and the data is read twice (the data is not destroyed).

[Problem to be solved by the invention]

As explained above, the read reset signal is shifted by half a cycle to avoid data destruction due to collision between writes and reads to the ES.

Because the data was read twice, a buffer slip alarm was sent.

However, even if there is no half-cycle shift (that is, even if a buffer slip does not occur), an alarm for the occurrence of a buffer slip may be sent out. A detailed explanation will be given below using FIG. 7.

First, in the same way as above, the OR gate 23 is activated in FIG.

When the read reset signal RR2 shown in (2) is ORed with the L part of the pulse A, an alarm as shown in FIG. 7 - [Phase] is sent out and the FF 31 is reset.

Therefore, the terminal Q of FF 31 becomes L, and correspondingly, the +12 ES read inhibit signal RI2 shown in Figure 7 - [Phase] becomes L, but since it is already in the , there is no change that the terminal Q becomes L.

Thereafter, the 8 clock synchronized with the line side clock shown in Figure 7-■
At the rising edge of the pulse R8, the terminal Q of the FF 31 becomes H, so the read inhibit signal RI2 shown in FIG.

In other words, a read prohibition signal! There is a problem in that an alarm may be sent even though 112 is not shifted by half a cycle, in other words, even though no buffer slip occurs.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 41.42 is the 1st. Data writing is controlled by the second write control signal, and the first. The first readout control signal controls the readout of data by the second readout control signal. In the second memory, 1 is a write control signal generation unit that generates the first and second write control signals using a first pulse synchronized with the device side clock, and 5 is a write control signal generation unit that is synchronized with the line side clock. The second pulse is used to generate the first pulse. Second
However, when a reset signal is input, the read control signal generating section holds the read control signal in the initial state until the next second pulse is input.

Further, 2 is a phase comparison part that compares the phase of the write control signal and the read control signal, and sends out an L level comparison result when the comparison result falls within a predetermined read access prohibited area; When the input comparison result is L level, uses the line side clock and the second clock to find a rising point that is later than the rising point of the second pulse adjacent to the L level comparison result. This is an alarm generation part that generates the alarm and the reset signal.

[Effect]

The present invention provides an alarm generation part to synchronize the pulse A shown in FIG. The generated generation signal is used to reset the alarm and the second pattern generation part.

Here, the rising point of this generated signal is delayed from the rising point of the second pulse synchronized with the line side clock, which is input immediately after the rising point of the pulse A.

Therefore, even if the second pattern generation section enters the operating state at the rising point of pulse R8, which is input immediately after the pulse R8, as in the conventional example, it is immediately reset at the rising point of the generated signal, so the buffer A slip occurs and an alarm is sent out.

That is, the occurrence of a buffer slip and the sending of an alarm coincide.

〔Example〕

FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2.

Note that the symbols on the left side of FIG. 3 indicate the waveforms corresponding to the same symbols in FIG. Also, the same reference numerals indicate the same objects throughout the figures.

Here, flip-flop 51. OR gate 52.5
3 is a component of the read control signal generation section 5, NAN
D gate 21. Flip-flop 22. OR gate 2
3 is a component of the phase comparison section 2, an inverter 61. Flip-flop 62. OR gate 63 indicates a component of alarm generation section 6.

The operation shown in FIG. 2 will be explained below with reference to FIG. still,
The operations of the write control signal generation section 1 and the read control signal generation section 5 have been explained in detail in the conventional example, so they will be briefly explained, and the sections according to the present invention will be explained in detail.

First, a pulse -8K (corresponding to the first pulse in the claims) is frequency-divided by 2 by a flip-flop (hereinafter abbreviated as FF) 11 to #I which is synchronized with the device side clock.
Write inhibit signal for ES 41 and #2 US 42 [1, [2 are generated and OR game] At 12°13, OR these two write inhibit signals and 8 and pulse -8 to create a write reset signal. WRI, WR
2 (see Figure 3-■ to ■).

Here, #IES and 112 ES correspond to the first memory and second memory in the claims.

Then, the signal obtained by NANDing the write inhibit signal old 1 and the read access inhibit signal 1sWIlli[+ is synchronized with the pulse 64, which is the line side clock, in the FF 22 (this synchronization signal is the A pulse of the conventional example). ) is added to the OR gate 23 (see FIG. 3 - ■, ■, ■).

On the other hand, pulse R8K (
(corresponding to the second pulse in the claims) as FF51
Divide the frequency by 2 and get Ill ES 41 and 112 ES 42
Read inhibit signal RI2. At the same time as generating R11, OR gates 12 and 13 are used to OR these two read inhibit signals and 8 and pulse R8 to generate read reset signals RR2 and RRI (see Figure 3).
(See [Phase]).

Then, by adding the read reset signal RR2 to the above OR gate and ORing it with the output of FF 22, a pulse 8" (which is the conventional alarm signal) as shown in Figure 3 - [Phase] is obtained. .

This pulse A° is pulse 1 at 64 which is the line side clock.
At 64 KS, it is taken into the FF 62 to obtain a pulse B as shown in FIG.

On the other hand, since the pulse R8 is also applied to the above-mentioned 8 which is inverted by the inverter 61, the OR with 1 pulse B is taken and a pulse as shown in Fig. 3-■ is obtained. This is used to reset the alarm and FF51.

Here, at the rising point of pulse R8 at 8 shown in Figure 3 - [Phase], the FF 51 operates and the terminal Q becomes H level, so the state of the read inhibit signal is reversed with respect to the previous state. However, since the FF 51 is immediately reset by the output of the OR gate (to the rising point of Figure 3 - ■), the FF 51
Terminal q becomes L level, and this state continues until the next pulse rise point at 8.

As a result, the states of the read inhibit signals R11 and RI2 are shifted by half a cycle as shown in FIG.

That is, the occurrence of a buffer slip always coincides with the sending of an alarm.

〔Effect of the invention〕

As described above in detail, one advantage of the present invention is that the occurrence of a buffer slip always coincides with the sending of an alarm.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, and FIG. 4 is a diagram showing an example of a clock transfer circuit. FIG. 5 is a circuit configuration diagram of a conventional example, FIG. 6 is an explanatory diagram of the operation of FIG. 5, and FIG. 7 is an explanatory diagram of problems in FIG. 5. In the figure, 1 is a write control signal generation part, 2 is a phase comparison part, 5 is a read control signal generation part, 6 is an alarm generation part, 41 is a first memory, and 42 is a second memory. Diagram M2 O of the practice of Mokuyumei's practice J Figure M2 O ■ [Phase] Figure 5 Room R fortress, explanatory diagram

Claims (1)

[Scope of Claims] First and second memories (4
1, 42), a write control signal generation unit (1) that generates the first and second write control signals using a first pulse synchronized with the device side clock, and a second write control signal generation unit (1) that generates the first and second write control signals using the first pulse synchronized with the device side clock. The first and second readout control signals are sent out using pulses, but when a reset signal is input, the readout control signal retains the readout control signal in the initial state until the next second pulse is inputted. A generation unit (5) is provided to convert data synchronized with the device side clock into data synchronized with the line side clock by alternately writing and reading data to and from the first and second memories. , a phase comparison part (2) that compares the phase of the write control signal and the read control signal and sends an L level comparison result when the comparison result falls within a predetermined read access prohibited area; When the comparison result is L level, an alarm having a rising point later than the rising point of the second pulse adjacent to the L level comparison result is generated using the line side clock and the second clock. and an alarm generation section (6) that generates the reset signal.