JPH0318349B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to nonvolatile semiconductor memories, and more particularly to row decoders. Non-volatile semiconductor memory uses floating gate type MOS- as memory cells.
They use nonvolatile elements such as FETs (insulated gate field effect transistors) or MNOS (metal nitrite oxide semiconductor) transistors, and floating gate memory cells are currently commonly used. As is well known, such non-volatile memory is
During writing, in addition to the normal power supply (5V), a program power supply (20V to 25V) is required to apply high voltage to the memory cells. For this reason, a voltage of, for example, 5V is applied to the row line directly connected to the gate of the memory cell, and a voltage of, for example, 25V is applied to the row line during reading and programming (writing), so special measures are required in the row decoder to handle this high voltage (25V). being done.

Figure 1 shows a general example of a row decoder in a non-volatile semiconductor memory, where 10 is the row decoder main body of the normal power supply (Vc = 5V) system, and 11 is writing to the row line of the memory cell array (not shown). A depletion type load transistor 12 is used to apply a high voltage of 25 V at the same time, and 12 is a connection point between the row line and the load transistor 11 and the row decoder main body 10.
This is a depletion type protection transistor with a drain-source path inserted between the output terminal of the transistor and the output terminal of the transistor. A high voltage of 25 V is applied to the drain of the load transistor 11 during writing, and a normal power supply of 5 V is applied during reading. Further, a /R signal of 0V is applied to the gate of the protection transistor 12 during writing, and a /R signal of 5V is applied during reading.

Therefore, in the above row decoder, the gate of the protection transistor 12 connected to the unselected row line at the time of writing is 0V, but at this time, the final stage transistor 1 of the row decoder main body 10
₀₁ is in the on state, it is discharged to 0V via the protection transistor 12. On the other hand, since the final stage transistor ₁₀₁ of the row decoder main body 10 corresponding to the row line in the selected state at the time of writing is in the off state, the output point N of the row decoder main body 10 is connected to the normal power supply potential through the depletion type transistor ₁₀₂ . Charges up to 5V. At this time, the protection transistor 12 connected to the selected row line
is in a cut-off state because its gate is at 0V but its source has risen to the potential of 5V at the output point N. Therefore, the row line in the selected state is charged to 25V through the load transistor 11 connected thereto. Since the high voltage of 25V on this row line is not applied to the corresponding row decoder main body 10, the row decoder main body 10 is constructed by increasing the channel length of the transistors used or taking special high voltage countermeasures. There's no need. However, through the load transistor 11, the
Since it is necessary to apply a potential of 25V, the threshold voltage Vth of this transistor 11 needs to be as low as possible. In other words, this transistor 11 is
Equivalently, a back gate bias of -25V is applied, and it must be turned on with this back gate bias of -25V. However, since the load transistor 11 and the protection transistor 12 as described above are manufactured in the same process using, for example, an N-channel process, their respective threshold voltages Vth are equal. Therefore, the threshold voltage Vth
If you try to apply a high voltage of 25V to the selected row line through the load transistor 11 by setting it low, the protection transistor 12 connected to this selected row line will not be sufficiently cut off, and the row decoder Current began to flow from the selected row line to the transistor ₁₀₂ of the main body 10, that is, the 5V power supply, and there were cases where high voltage was not applied to the selected row line. This kind of thing is
This was particularly problematic when the operating power supply of the row decoder main body 10 was lower than 5V. Contrary to the above, if the threshold voltage Vth of both transistors 11 and 12 is set a little higher, the protection transistor 12 connected to the selected row line will be sufficiently cut off, but the threshold voltage Vth of the load transistor 11 will be lowered due to the back gate bias.
Due to the increase in Vth, high voltage 25V is no longer applied to the selected row line. As mentioned above, load transistor 1
In a conventional row decoder in which the protection transistor 1 and the protection transistor 12 are manufactured in the same process, it is necessary to compromise the characteristics of both transistors 11 and 12 at a certain point, and if the threshold voltage Vth varies even slightly due to the process, the write At times, a sufficient high voltage is no longer applied to the selected row line, resulting in a defect that takes a long time to write to the memory cell. In other words, conventionally the threshold voltage of both transistors 11 and 12
There was a problem in that the Vth had to be controlled with great care, and the process margin was reduced.

The present invention was made in view of the above circumstances, and
By setting the threshold voltage Vth ₂ of the protection transistor to an appropriate value higher than the threshold voltage Vth ₁ of the load transistor, a sufficiently high voltage can be applied to the selected row line during writing, and the protection transistor can be sufficiently cut off. The present invention provides a nonvolatile semiconductor memory with a large process margin.

In the memory of the present invention, the circuit configuration of the row decoder is the same as that shown in FIG. 11 threshold voltage Vth ₁ is made sufficiently low, and the threshold voltage of protection transistor 12 is
Vth ₂ is set to be higher than the threshold voltage Vth ₁ of the load transistor 11.

That is, in the present invention, Vth ₂ of the protection transistor 12 is set in the range of -2V to -0.3V. In the normal N-channel process,
Even if the transistor channel does not require any modification (ion implantation process), for example, if a 20Ωcm P-type substrate is used, its surface charge can be reduced.
With Q _SS , the threshold voltage of the transistor can be achieved at around -0.3V. Of course, the threshold voltage may be set to an optimal value within the range of -2 to -0.3V by appropriately performing ion implantation.

In this way, in the circuit shown in FIG. 1, if the threshold voltage Vth ₂ of the protection transistor 12 is, for example, -0.5V, the /R signal is 5V at the time of reading, so the output terminal N of the row decoder main body 10 is 5V (selected state ) or 0V (non-selected state), the selected row line is charged by the normal power supply (5V) and the non-selected row line is discharged to 0V.
On the other hand, even if the /R signal is 0V at the time of writing, the protection transistor 12 connected to the unselected row line is sufficiently turned on, and the unselected row line is discharged to 0V and connected to the selected row line. The protection transistor 12 is sufficiently cut off and the selected row line is charged to a sufficiently high voltage through the load transistor 11 connected thereto whose threshold voltage Vth ₁ is sufficiently low. Therefore, since the high voltage of this selected row line is not applied to the corresponding row decoder body 10, the row decoder body 10 does not require any special measures against high voltage.

Note that even if the level of the /R signal applied to the gate of the protection transistor 12 is not 0V as in the example above during writing, it is sufficient as long as it is somewhat lower than the level during reading (normal power supply potential); for example, 4V.
To a certain degree, the row decoder main body 10 is safe.
That is, the protection transistor 12 connected to the selected row line has its source (row decoder body 10
If _the output point (N) of To-
A voltage of 1V will be applied to it, and it will never conduct. In other words, during writing, the value of the /R signal supplied to the gate of the protection transistor 12 is determined by the voltage that is the sum of the voltage at the output point N of the row decoder body 10 at the time of selection and the threshold voltage of the protection transistor 12. It is also good if it is set low. Further, in this way, the gate of the protection transistor 12 is biased to a predetermined potential.
Since the breakdown voltage due to the electric field between the drains is increased, there is an advantage that there is less concern about breakdown due to high voltage during writing.

As mentioned above, as an example of a control signal generation circuit for supplying the /R signal, which has a desired voltage of 5 V during reading and a desired voltage in the range that cuts off the protection transistor 12 during writing, the second control signal generation circuit has a relatively simple configuration. As shown in the figure. That is, 21 is an enhancement type transistor, and 22 is a depletion type transistor, each of which is, for example, an N-channel transistor. The above transistor 21
The source of the transistor 22 is grounded, and the source and gate of the transistor 22 are connected to the drain thereof, and the drain of the transistor 22 is normally connected to the power supply Vc. Then, 0V is applied to the gate of the transistor 21 during reading, and 5V is applied during writing. Therefore, during readout, transistor 2
1 is turned off, and the normal power supply potential of 5V is output to the drain of this transistor 21 through the transistor 22. Also, during writing, transistor 2
An output determined by the ratio of the on-resistances of 1 and 22 (this is variable by arbitrarily setting the above-mentioned resistance ratio; for example, 4V) is generated.

As described above, according to the non-volatile semiconductor memory of the present invention, the threshold voltage of the load transistor is lowered and the threshold voltage of the protection transistor is set to an appropriate value higher than the threshold voltage of the load transistor, so data can be written. Sometimes a sufficiently high voltage can be applied to the selected row line through the load transistor and the protection transistor can be cut off sufficiently to prevent the decoder from applying high voltage to the body through the protection transistor. Since the load transistor and the protection transistor are each set to a desired threshold voltage in this way, there is an advantage that the process margin is large compared to the conventional method of setting threshold voltages that compromise the characteristics of both transistors.

Furthermore, since a desired voltage lower than that during data reading can be applied to the gate of the protection transistor during data writing, a desired cut-off bias can be applied during data writing in relation to the threshold voltage of the protection transistor. Further, a circuit for generating such a desired control voltage can be realized with a simple configuration using one enhancement type transistor and one depletion type transistor.

As described above, the present invention can provide a nonvolatile semiconductor memory that can apply a sufficiently high voltage to a selected row line during data writing, can sufficiently cut off a protection transistor, and has a large process margin.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a row decoder of a general non-volatile semiconductor memory, and FIG. 2 is an example of a control signal generation circuit for supplying a control signal /R to the row decoder of a memory according to the present invention. FIG. 10...Row decoder main body, 11...Load transistor, 12...Protection transistor.

Claims (1)

[Claims] 1. A row line connected to the gate of a nonvolatile memory cell, one end of which is connected to the row line, the other end of which is applied with a predetermined high voltage during writing, and has a negative threshold voltage. A load transistor and a source-drain path are connected between the output terminal of the decoder and the row line, and have a negative threshold voltage, and the threshold voltage is set higher than that of the load transistor, and when reading, a first high voltage is set. a protection transistor whose gate is supplied with a second high logic level voltage whose logic level voltage is higher than the low logic level voltage and lower than the first high logic level voltage during writing; The second high logic level voltage supplied to the gate of the transistor is set lower than the sum of the voltage at the output terminal of the decoder at the time of selection and the threshold voltage of the protection transistor. Non-volatile semiconductor memory.