JPH0318373B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a skew adjustment circuit, and in particular, uses a voltage-controlled delay circuit as a delay element, inputs signals at two points to be skew-adjusted to a phase comparison circuit, and adjusts the phase comparison circuit. By digitally controlling the voltage-controlled delay circuit based on the output, a phase-lock loop circuit can be configured, configured as desired, and adjusted to the required delay time easily and with high precision. The present invention relates to a skew adjustment circuit configured to obtain the skew adjustment circuit.

Conventionally, when attempting to adjust delay time for skew adjustment in digital logic circuits, etc.,
For example, one method, as shown in Figure 1, is to use a delay circuit (DLY) with multiple output terminals for adjustment, and to make adjustments by selecting the output terminals as appropriate. . In this case, not only is the operation of selecting and connecting the terminals troublesome, but also the desired delay time may not be obtained when making minute adjustments. Another method, as shown in Figure 2, is to use a cable line and create a cable line with a length that provides the desired delay time between the elements, but in this case, the circuit discrete This was a factor that hindered the development of

An object of the present invention is to solve the above-mentioned problems and realize a skew adjustment circuit that is easy to adjust and can obtain a highly accurate delay time. A voltage control delay circuit is provided in front of the first point and the second point where the skew adjustment is to be performed, and the point that requires a signal delay is provided, and the signals at the first and second points are set to the shortest or equal length, respectively. A phase comparator input via a long line, an up/down counter whose counting direction is controlled by the output of the phase comparator, and an up/down counter whose output is converted into an analog signal and which is connected to the voltage controlled delay circuit. The delay control signal is configured by a D/A conversion circuit that supplies the up-up signal so as to match the phase of the signal input to the phase comparator.
The present invention is characterized in that a desired skew adjustment delay time is obtained in the voltage controlled delay circuit by controlling the counting direction of the down counter.

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 3 is a block diagram of the skew adjustment circuit of the first embodiment according to the present invention, in which 1 is a voltage controlled delay circuit (VCD), 2 is a phase comparator, 3 is a charge pump circuit, and 6 to 10 are Logic gate circuit, points A and B are the points where skew adjustment should be made, _l1 is the line length from point A to one input of phase comparator 2, _l2 is the line length from point B to the other input of phase comparator 2 This is the line length up to the end. In the embodiment, the line length l ₁ and the line length l ₂ are made equal lengths. 11 is an up/down control circuit, 1
2 is an up/down counter, and 13 is a D/A conversion circuit. In the embodiment shown in FIG. 3, a phase comparator 2, an up/down control circuit 11, an up/down counter 12, a D/A conversion circuit 13,
The voltage control delay circuit 1, logic gate circuit 8, and phase comparator 2 constitute a phase lock loop circuit, where the signal at point A is the reference frequency signal and the signal at point B is the frequency signal to be locked. It corresponds to

In the embodiment of the present invention, when the phase of point B is ahead of the phase of point A, the D/A conversion circuit 13
Control is performed to increase the delay time of the voltage-controlled delay circuit 1 by the output voltage of the voltage-controlled delay circuit 1. While the phase of point B is ahead of the phase of point A, the control voltage is simply sent out from the D/A conversion circuit 13 in the direction of increasing the delay time of the voltage control delay circuit 1, thereby sequentially The phase difference between point A and point B decreases. In this way, phase synchronization control is performed, and when the phases of the two input signals to the phase comparator 2 become equal,
The output voltage of the D/A conversion circuit 13 is made to settle at a constant value. As a result, voltage control delay circuit 1
In this case, the required delay time can be obtained.

Here, up/down control circuit 1
1. The circuit portion consisting of the up/down counter 12 and the D/A conversion circuit 13 has a novel configuration not found in conventional phase lock loop circuits. This is achieved with high precision and stability by digitally controlling the control voltage generation section. Therefore, it is possible to perform delay time adjustment with higher accuracy and stability than in the conventional configuration.

The operation of the phase lock loop circuit used in the embodiment shown in FIG. 3 will be explained below with reference to other drawings. FIG. 4 is a block diagram of a phase lock loop circuit according to an embodiment of the present invention, in which 100 is a phase comparator, 110 is an up/down control circuit, and 120 is an up/down control circuit.
Down counter, 130 is a D/A conversion circuit, 14
0 is a voltage controlled delay circuit (VCD), f ₁ is a reference frequency, f ₂ is a frequency to be locked which is the output of the voltage controlled delay circuit 140, 150 is a lead signal line, 160 is a delay signal line, 170 is a clock signal line, 180 is an up/down instruction signal line. 5 is a detailed diagram of the up/down control circuit 110 shown in FIG. 4. In the figure, the same numbers as in FIG. 4 are the same, 190 is a clock generation circuit, 200 is an inverter, 210 and 220 are AND circuits, and 230 is a NOR circuit.

The operation shown in FIG. 4 will be explained below. Phase comparator 1
00 is the same as the conventional circuit, and the reference frequency
This is to compare the phase of f ₁ and the lock target frequency f ₂ , and when both frequencies f ₁ and f ₂ are equal, the f ₁
A signal with a pulse width corresponding to the phase difference between and f ₂ is output. In the example, the reference frequency is
When the phase of f ₁ leads the locking target frequency f ₂ , a leading signal with a pulse width corresponding to the phase difference is output on the leading signal line 15, and the phase of the reference frequency f ₁ leads the locking target frequency f _{2 .} When you are later than
A delayed signal having a pulse width corresponding to the phase difference is output onto the delayed signal line 160.

In addition, the up/down controller circuit 110
A clock generation circuit 190 within the circuit constantly outputs, for example, a clock pulse with a period of several μs and a duty of 50%. The clock output from the clock generation circuit 190 is sent to the up/down instruction signal line 180 through the inverter 200 and is input to the up/down instruction terminal of the up/down counter 120. In the example,
When the level on the up/down instruction signal line 180 is low (“0”), the up/down counter 120 is instructed to count up, and the level on the up/down instruction signal line 180 is high (“1”). When the level is reached, the up/down counter 120 is instructed to count down.

Now, the phase of the reference frequency f ₁ is the frequency to be locked.
f ₂ and a lead signal is output on the lead signal line 150, the level of the direct output clock from the clock generation circuit 190 is at a high level, and the level of the up/down instruction signal is inverted. When instructing to count up on the line 180, the output of the AND circuit 210 is set to "1" and a clock pulse (negative polarity) is sent to the up/down counter 120. As a result,
The down counter 120 increments by +1. Therefore, the output value of the D/A converter circuit 130 receiving the output of the up/down counter 120 increases by one step, giving a larger voltage value to the voltage control delay circuit 140. Therefore, the delay time of the voltage control delay circuit 140 becomes a smaller value, and the phase of the lock target frequency _f2 advances by a predetermined amount, after which this operation is repeated.

Next, when the clock from the clock generation circuit 190 is inverted and becomes a low level, if the advance signal is still being output on the advance signal line 150, the advance clock to the up/down counter 120 is It is not created, and the state of the up/down counter 120 does not change. Then, when the clock is inverted and the direct output clock from the clock generation circuit 190 becomes high level,
As mentioned above, the up/down counter 120
Based on this, the output value of the D/A conversion circuit 13 is further increased by one step, and the phase of the lock target frequency f ₂ output from the voltage control delay circuit 140 is further advanced by a predetermined amount. ,
This operation is repeated thereafter. In this way, the phase of the lock target frequency _f2 gradually approaches the phase of the reference frequency _f1 , and when the two phases match,
The phase comparator 100 no longer outputs either a delayed signal or a lead signal, resulting in a stable state.

Next, the phase of the reference frequency f ₁ is the frequency to be locked.
f ₂ and a delayed signal is output on the delayed signal line 160, the level of the direct output clock from the clock generation circuit 190 is low, and the level-inverted up/down instruction is output. When a countdown is instructed on the signal line 180, the output of the AND circuit 220 is set to "1" and a clock pulse (negative polarity) is sent to the up/down counter 120. As a result, the up/down counter 120 increments by -1 step.
Therefore, the output value of the D/A conversion circuit 130 receiving the output of the up/down counter 120 decreases by one step, giving a smaller voltage value to the voltage control delay circuit 140. Therefore, the delay time of the voltage control delay circuit 140 becomes a larger value,
The phase of the lock target frequency _f2 is delayed by a predetermined amount, and this operation is repeated thereafter.

Next, when the clock from the clock generation circuit 190 is inverted and becomes high level, if the delay signal is still output on the delay signal line 160, the step clock to the up/down counter 120 is not generated. UP/DOWN COUNTER 1
The state of 20 remains unchanged. Then, the next time the clock is inverted and the direct output clock from the clock generation circuit 190 becomes a low level state, the up/down counter 120 is -
Based on this, the output value of the D/A conversion circuit 130 is further decreased by one step.
The delay time of the voltage control delay circuit 140 becomes larger, the phase of the lock target frequency _f2 is further delayed by a predetermined amount, and this operation is repeated thereafter. In this way, the phase of the lock target frequency f ₂ approaches the phase of the reference frequency f _{1 one} after another, and when the two phases match, neither the delay signal nor the lead signal is output from the phase comparator 100, resulting in a stable state. becomes.

As explained above, according to the embodiment,
Using a down counter and a D/A conversion circuit, the counting direction of the up/down counter is changed according to the phase difference, and the voltage control delay circuit is controlled by the D/A conversion circuit, which improves adjustment accuracy. Since this is determined by the number of bits of the D/A conversion circuit, a high-performance phase lock loop circuit can be used and highly accurate adjustment can be performed. Furthermore, in the embodiment, by providing the up/down counter 12 with a lock function, it is possible to perform adjustment operations periodically, and once the adjustment is completed, the up/down control circuit is connected to the phase comparator 2. 11 can be removed from the network.

As explained above, according to the present invention, a voltage controlled delay circuit is used as a delay element, and the voltage controlled delay circuit is incorporated into a phase lock loop circuit to automatically adjust the delay time. This makes it possible to perform easy and highly accurate skew adjustment, which is extremely effective.

[Brief explanation of the drawing]

1 and 2 are conventional skew adjustment circuits, FIG. 3 is a block diagram of a skew adjustment circuit according to an embodiment of the present invention, FIG. 4 is a block diagram for explaining the circuit operation of an embodiment, and FIG. The figure is a detailed diagram of the up/down control circuit. In the figure, 1 is a voltage controlled delay circuit, 2 is a phase comparator, 5 is a DC amplifier, and 13 is a D/A conversion circuit.

Claims (1)

[Claims] 1. A voltage control delay circuit is provided before the point where signal delay is required between the first point and the second point where skew adjustment is to be performed in the logic circuit network, and A phase comparator into which signals are input through lines of the shortest or equal length, an up/down counter whose counting direction is controlled by the output of the phase comparator, and a converter that converts the output of the up/down counter into an analog signal; It is constituted by a D/A conversion circuit that provides a delay control signal to the voltage-controlled delay circuit, and controls the counting direction of the up/down counter so as to match the phase of the signal input to the phase comparator. A skew adjustment circuit characterized in that a desired skew adjustment delay time is obtained in the voltage controlled delay circuit.