JPH03185861A - Constitution of logic integrated circuit - Google Patents

Abstract

PURPOSE:To increase the number of gates capable of being loaded on chips in the same size without augmenting skews and decreasing working speed by using an SPL circuit as a gate having a large load and an NTL circuit as a gate having a small load. CONSTITUTION:Striplike cell regions 4a and channel regions 4b are formed alternately. Signal conductors connecting each gate are disposed in the channel regions 4b. Macro cells 5 in which two SPL gate cells 5a and two NTL gate cells 5b are combined are arranged in a lateral line in the cell region 4a. When desired logic is constituted in gate arrays composed of SPL gates and NTL gates, the SPL gates and NTL gates are used properly in response to the magnitude of load. That is, the NTL gates are employed as gates having small load capacitance CL, and the SPL gates are employed as gates having large load capacitance CL. Accordingly, when the NTL gates have small load capacitance, working speed thereof is increased fast enough not to cause any skew.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuit technology and to technology that is particularly effective when applied to basic logic gates of bipolar logic integrated circuits, such as NTL having an active pull-down circuit.
(Non-Threshold Logic) circuits are used as basic gates in gate arrays.

[Prior art] As a bipolar transistor type gate array, ECL
(Emitter-coupled logic) circuits as basic gates and NTL circuits as shown in FIG. 4 as basic gates have been proposed.

Conventionally, the output stage of both the ECL circuit and the NTL circuit has been configured with an emitter follower to drive a load. In a gate circuit having such an emitter follower as an output stage, an active element (transistor) raises the output to a high level, but a static element (resistance) lowers the output to a low level. Therefore, the switching time is different when the output rises and when the output falls, resulting in a drawback that skew is likely to occur.

Therefore, an ECL gate circuit called an ECL turbo has been proposed, in which the output stage is composed of an active pull-up circuit consisting of an emitter follower transistor and a capacitively coupled active pull-down circuit ("Nikkei Electronics", 1989, 2 (See Monthly issue, pp. 213-214).

In addition, as an NTL circuit designed to speed up switching from high level to low level, the applicant has previously developed and proposed an NTL circuit with an active pull-down circuit as shown in FIG. No. 274170).

That is, the emitter follower transistor Q1 . In place of the emitter resistor between the emitter terminal of the emitter terminal and the power supply voltage terminal VTT, a pull-down transistor Q l m is connected, and the transistors Q l l to Q1 . C to the common emitter terminal of
A differentiating circuit R is connected to detect the level change, and when the output falls, the output of the differentiating circuit is used to pull down the transistor Q.
By temporarily turning on tm, the change to low level is made faster.

[5@Problem that Akira is trying to solve] By the way, the above NTL with active pull-down circuit
Although skew can certainly be reduced in circuits,
It has been found that there is a problem in that the hazard is amplified when these are connected in multiple stages.

In addition, gate arrays whose basic gates are NTL circuits with active pull-down circuits (hereinafter abbreviated as SPL circuits) can be mounted on a chip of the same size compared to gate arrays whose basic gates are ordinary NTL circuits. The problem was that there were only a few.

An object of the present invention is to provide a gate array configuration technique that can reduce hazard without increasing skew.

Another object of the present invention is to provide a gate array configuration technique that allows the number of gates to be mounted on a chip of the same size without increasing skew or reducing operating speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

The present inventors have found that in combinational logic using SPL circuits, hazards can be reduced by inserting NTL circuits at locations where SPL circuits are connected in multiple stages. Furthermore, in a gate array, not all gates have the same load, and there are gates with very small loads, and it has been found that even if an NTL circuit with a small driving force is used there, skew does not occur.

This invention was made based on the above knowledge, and it is possible to configure a gate array by combining SPL circuit cells and NTL circuit cells, or to use aluminum wiring as necessary in a gate array having an SPL circuit as a basic gate. NT using some of the elements in the SPL circuit cell by changing
This proposal proposes configuring an L circuit.

[Function] According to the above-described means, by inserting an NTL circuit at a location where SPL circuits are connected in multiple stages, it is possible to prevent the occurrence of a hazard without increasing skew.

Also, depending on the load size of each gate, the SPL circuit is installed on the gate with a large load, and the N
By using TL circuits, it is possible to increase the number of gates that can be mounted on a chip of the same size without increasing skew or reducing operating speed.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a gate array.

In FIG. 1, 1 is a semiconductor chip, 2 is a bonding pad as an input/output terminal arranged around the periphery of the chip,
3 is an input circuit 3a and an output circuit 3b corresponding to each bad 2.
Input circuit 3 is an input/output circuit section in which
Either one of the output circuit a and the output circuit 3b is connected to the pad 2 as a corresponding input/output terminal.

Further, 4 is an internal logic section in which, although not particularly limited, strip-shaped cell regions 4a and channel regions 4b are alternately provided. The channel region 4b is a region where signal lines connecting gates are provided. In this embodiment, two SPL gate cells 5a and two NTL gate cells 5b are provided in the cell area 4a as shown in FIG. 2(A) or (B).
Macro cells 5, which are a combination of the following, are arranged in a horizontal row.

Since the NTL circuit (Fig. 4) has fewer elements and smaller cell area than the SPL circuit (Fig. 3), the gate array of the embodiment is the same as the gate array constructed using only SPL gates. More gates can be placed in the area.

When configuring a desired logic using a gate array made up of SPL gates and NTL gates as described above, the SPL gates and NTL gates are selectively used depending on the size of the load. In other words, NTL is applied to the gate with small load capacitance CL.
SP is used for gates with large load capacitance CL.
Use L gate.

Here, the standard for the size of the load is l, OpF, and CL is 1. When smaller than OpF, use NTL gate,
Also C Shiga 1. When it is larger than OpF, an SPL gate may be used.

When NTL gates and SPL gates are used selectively as described above, skew does not occur because the NTL gate has a sufficiently high speed when the load capacitance is small. Also,
Since the NTL gate is interposed between the SPL gates, it is possible to prevent hazard amplification that occurs when SPL gates are connected in multiple stages.

FIG. 3 shows an example of the above SPL circuit. That is, three input transistors Q, , Q1m'l
Qts is in parallel form, that is, the collector terminal and emitter terminal are commonly connected to each other, a resistor RC is connected between the common collector terminal and the power supply voltage Vcc (ground point), and a resistor RC is connected between the common emitter terminal and the voltage Vcc (ground point). t1! A resistor Re is connected between the voltage terminal VEEi and the voltage terminal VEEi.
are connected to constitute an input stage 11. Output stage 12
is formed by transistors QMI, Q, and 8 connected in series between power supply voltage Vcc and VTT.

The base terminal of the emitter follower transistor Qm + constituting the output stage is connected to a connection node n1 between the common collector of the input transistors Q l l to Ql m and the resistor Rc.

Also, between the power supply voltage VCc and VTT, a transistor Q, .
and resistor R1 are connected in series, and their connection node n
, the pull-down transistor Q of the output stage 12,
The base terminal of YO is connected. Above transistor Q
, 1 has a constant voltage VB applied to its base terminal, and functions as a biasing means for the transistor Q-. In this case, the bias point of the transistor Qlm is determined by the base voltage VB and the value of the resistor R1. Along with this,
A capacitor C1 is connected between a connection node n between the bias transistor Qa + and the resistor R8 and a common emitter terminal n1 of the input stage 11. This capacitor C1 and the resistor R1 constitute a differentiating circuit that detects a change in the level of the node n.

Furthermore, in this embodiment, the clamping transistors Q and O for fixing the high level of the output are connected to the power supply voltage terminal V
cc and the output terminal OUT. A constant voltage VB is applied to the base terminals of the transistors Q, 1, so that the high level of the output Vout is higher than that of the transistors Q1. The voltage is clamped to a lower potential by the base-emitter voltage VBE.

In the embodiment described above, SPL gate cells and NTL gate cells are mixed on the same chip and used depending on the situation, but the gate array is composed only of SPL gate cells. Then, where an NTL gate is desired, an NTL gate is constructed by changing the aluminum wiring and using only a part of the elements in the SPL gate cell. In other words, an NTL circuit as shown in FIG. 4 can be constructed by configuring the gate without using the elements surrounded by the chain line a in FIG. 3.

Note that the SPL circuit constituting the gate array of the above embodiment is not limited to the circuit type shown in FIG. and its emitter side resistor R1 can be omitted, or the pull-down transistor Q
It may be a circuit in which a resistor is inserted on the emitter side of , so that a small current is constantly flowing.

Furthermore, in the above embodiment, an SPL gate is used as the output circuit 3b constituting the input/output circuit section 3, and an ECL gate is used as the input circuit 3a, thereby making it difficult for external noise to be transmitted to the internal logic section 4. It is recommended to configure it as follows.

As explained above, in the above embodiment, the SPL circuit cell and the N
TL circuit cells can be combined to form a gate array, or
In a gate array whose basic gate is an SPL circuit,
By changing the aluminum wiring as necessary, some of the elements in the SPL circuit cell constitute an NTL circuit, so by inserting the NTL circuit at the point where the SPL circuit is connected in multiple stages, the skew can be reduced. It is possible to prevent the occurrence of hazards without increasing the

Also, depending on the load size of each gate, the SPL circuit is installed on the gate with a large load, and the N
The use of a TL circuit has the effect of increasing the number of gates that can be mounted on a chip of the same size without increasing skew or reducing operating speed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, S
Although a gate array in which a PL circuit and an NTL circuit are mixed has been described, an ECL circuit or an ECL turbo may be mixed in addition to the above.

In the above explanation, the invention made by the present inventor was mainly applied to gate arrays, which is the background application field, but this invention is not limited to this, and the invention is not limited to that, but is applicable to logic integration using SPL circuits. Can be used for general circuits.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, N with an active pull-down circuit added.
In a gate array whose basic gate is a TL circuit, it is possible to prevent the occurrence of hazards without increasing skew, and it is also possible to mount more gates on a chip of the same size.

[Brief explanation of drawings]

FIG. 1 is a layout configuration diagram showing an example of applying the present invention to a gate array, FIG. 2 is an explanatory diagram showing an example of the configuration of a basic gate cell in a logic section, and FIG. A circuit diagram showing an example of the developed NTL circuit with an active pull-down circuit. FIG. 4 is a circuit diagram showing an example of the NTL circuit. 1... Semiconductor chip, 2... Pad, 3...
・Input/output circuit section, 11...input stage, 12...output stage, Ql l~QI1...input transistor, Ql+...emitter follower transistor,
Q, 1...Pull-down transistor, Q□...
・Bias transistor, Qo...clamp transistor. Figure 1 Figure (A) (B) 0 Figure Figure

Claims (1)

[Claims] 1. NTL (non-threshold logic circuit);
In a logic integrated circuit in which a logic gate formed by connecting an active pull-down circuit to the output stage of an NTL circuit is mixed, the NTL circuit is used in parts with a small load, and the logic gate with an active pull-down circuit is used in parts with a large load. A method for configuring a logic integrated circuit, characterized in that the method is used. 2. In a logic integrated circuit whose basic gates are an NTL circuit and a logic gate formed by connecting an active pull-down circuit to the output stage of the NTL circuit, one of the elements in the basic gate cell is changed in areas with a small load due to wiring changes. N in the department
1. A method for configuring a logic integrated circuit, comprising configuring a TL circuit.