JPH03185869A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH03185869A
JPH03185869A JP1325026A JP32502689A JPH03185869A JP H03185869 A JPH03185869 A JP H03185869A JP 1325026 A JP1325026 A JP 1325026A JP 32502689 A JP32502689 A JP 32502689A JP H03185869 A JPH03185869 A JP H03185869A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
molecular
semiconductor integrated
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1325026A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1325026A priority Critical patent/JPH03185869A/en
Publication of JPH03185869A publication Critical patent/JPH03185869A/en
Pending legal-status Critical Current

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Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体集積回路装置と分子素子集積回路装置の
ハイブリッド徊成法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for hybrid fabrication of semiconductor integrated circuit devices and molecular element integrated circuit devices.

[従来の技術] 従来、半導体集積回路装置と分子素子集積回路装置とは
各々独立に製作、開発され、一つの基板内にハイブリッ
ド化されたものはなかった。
[Prior Art] Conventionally, semiconductor integrated circuit devices and molecular element integrated circuit devices have been manufactured and developed independently, and none have been hybridized within a single substrate.

[発明が解決しようとする課題] 上記従来技術によると、半導体集積回路装置と分子レベ
ルでの加工を要する分子素子集積回路装置とのハイブリ
ッド化は困難であると云う課題があった。
[Problems to be Solved by the Invention] According to the above-mentioned prior art, there is a problem in that it is difficult to hybridize a semiconductor integrated circuit device and a molecular element integrated circuit device that requires processing at the molecular level.

本発明はかかる従来技術の課題を解決し、半導体集積回
路装置と分子素子集積回路装置を容易に一つの基板内に
ハイブリッド化する新らしい構造を提供する事を目的と
する。
It is an object of the present invention to solve the problems of the prior art and to provide a new structure that easily hybridizes a semiconductor integrated circuit device and a molecular element integrated circuit device within one substrate.

[課題を解決するための手段] 上記課題を解決するために、本発明は半導体集積回路装
置に関し、半導体集積回路装置表面の限定された領域に
分子素子集積回路を形成し、該分子素子集積回路のポリ
アセチレン等から成る分子電極と、前記半導体集積回路
装置に形成された金属電極とを結線する手段を取る。
[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a semiconductor integrated circuit device, in which a molecular element integrated circuit is formed in a limited area on the surface of the semiconductor integrated circuit device, and the molecular element integrated circuit is A means is taken to connect a molecular electrode made of polyacetylene or the like with a metal electrode formed on the semiconductor integrated circuit device.

[実施例] 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.

第1図乃至第3図は本発明の実施例な示す半導体集積回
路基板表面に分子素子集積回路装置を形成したハイブリ
ッド集積化装置の要部の断面図である。
1 to 3 are cross-sectional views of essential parts of a hybrid integrated device in which a molecular element integrated circuit device is formed on the surface of a semiconductor integrated circuit substrate according to an embodiment of the present invention.

第1図では、Set基板11.拡散層12.ゲート酸化
膜15.ゲート電極14及びSin、膜15等から成る
半導体集積回路装置基板の前記Si基板110表面の前
記310.[15に窓開けした領域に分子素子集積回路
装置17を形成し、該分子素子集積回路装置17には、
分子−つ一つに記憶保持やスイッチ動作などの機能を持
たせた分′f−機能素子18とこれに連らなったポリア
セチレン等から成る分子電極19及び19′と、絶縁分
子等が埋め込まれて成り、前記分子電極19及び19′
は前記半導体集積回路装置基板の表面に形成されたPt
、At、Ti、W、Si等から成る金属電極16及び1
6′や前記拡散層12かも成る配線層と結線されて成る
In FIG. 1, Set substrate 11. Diffusion layer 12. Gate oxide film 15. The 310. [A molecular device integrated circuit device 17 is formed in the area opened in 15, and the molecular device integrated circuit device 17 includes:
Each molecule has a function such as memory retention or switch operation. A functional element 18 is connected to molecular electrodes 19 and 19' made of polyacetylene, etc., and insulating molecules are embedded. The molecular electrodes 19 and 19'
is Pt formed on the surface of the semiconductor integrated circuit device substrate.
, At, Ti, W, Si, etc., metal electrodes 16 and 1
6' and the diffusion layer 12 are also connected to a wiring layer.

第2図では、Si基板21.拡散層22.ゲート酸化膜
23.ゲート電極24及びSin、膜25等から成る半
導体集積回路装置基板の前記5iO1膜250表面の限
定された領域に分子素子集積回路装置27を形成し、該
分子素子集積回路装置27は分子機能素子28や絶縁分
子あるいはポリアセチレン等から成る分子電極29及び
29′等によって構成されて成り、該分子電極29及び
29′等は、前記半導体集積回路基板表面等に形成した
金属電極26及び26′等と結線されて成る。尚、分子
素子集積回路装置27は、半導体集積回路装置基板に形
成されているトランジスタ等9機能素子の上に形成され
ても良い事は云うまでもない。
In FIG. 2, a Si substrate 21. Diffusion layer 22. Gate oxide film 23. A molecular element integrated circuit device 27 is formed in a limited area on the surface of the 5iO1 film 250 of a semiconductor integrated circuit device substrate consisting of a gate electrode 24, a sin film 25, etc., and the molecular element integrated circuit device 27 has a molecular functional element 28. The molecular electrodes 29 and 29' are made of insulating molecules, polyacetylene, etc., and the molecular electrodes 29 and 29' are connected to metal electrodes 26 and 26' formed on the surface of the semiconductor integrated circuit board, etc. It consists of being done. It goes without saying that the molecular element integrated circuit device 27 may be formed on nine functional elements such as transistors formed on a semiconductor integrated circuit device substrate.

第5図では、81基板51.拡散層52jゲートぼ化d
i、sseゲート電極54及びS i O,膜55から
成る半導体集積回路装置基板の拡散層52かも連もなっ
て形成された金属電極37上に分子素子集積回路装置3
7を絶縁膜40に囲まれた領域に形成したもので、前記
分子素子集積回路装置は、分子機能素子38や絶縁分子
及び分子電極39及び39′等から成り、該分子電極3
9は下地の金属電5Ii56と結線されて成り、分子電
極59′は、絶縁膜40の上部に形成された、金属電極
36′と結線されて成る。
In FIG. 5, 81 substrates 51. Diffusion layer 52j gate blur d
The molecular element integrated circuit device 3 is formed on the metal electrode 37 formed in series with the diffusion layer 52 of the semiconductor integrated circuit device substrate consisting of the i, sse gate electrode 54 and the SiO, film 55.
7 is formed in a region surrounded by an insulating film 40, and the molecular element integrated circuit device is composed of a molecular functional element 38, insulating molecules, molecular electrodes 39 and 39', etc.
9 is connected to the underlying metal electrode 5Ii 56, and the molecular electrode 59' is connected to the metal electrode 36' formed on the upper part of the insulating film 40.

[発明の効果] 本発明により、従来技術により形成された半導体集積回
路装置基板上に容易に分子−つ一つを集積化して構成す
る分子素子集積回路装置をハイブリッド構成することが
できる効果がある。
[Effects of the Invention] The present invention has the effect that it is possible to easily construct a hybrid molecular element integrated circuit device by integrating each molecule on a semiconductor integrated circuit device substrate formed by a conventional technique. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は本発明の実施例を示す半導体集積回
路基板表面に分子素子集積回路装置を形成したハイブリ
ッド集積化装置の要部の断面図である。 t1*21.!M・・・・・・Si基板12會22,5
2・・・・・・拡散層 15.25.55・・・・・・ゲート酸化膜4.24.
34・・・・・・ゲート電極5.25,55・・・・・
・slo、  膜6.16’  、26.26’  、
56.’56’  ・・・・・・・・・金属電極 7.27.57・・・・・・分子素子集積回路装置8.
28.58・・・・・・分子機能素子9.1.9’ 、
29.29’ 、59.59’・・・・・・・・・分子
電極 0・・・・・・・・・・・・・・・・・・・・・・・・
絶縁膜以上
1 to 3 are cross-sectional views of essential parts of a hybrid integrated device in which a molecular element integrated circuit device is formed on the surface of a semiconductor integrated circuit substrate, showing an embodiment of the present invention. t1*21. ! M...Si substrate 12 22,5
2...Diffusion layer 15.25.55...Gate oxide film 4.24.
34... Gate electrode 5.25, 55...
・slo, membrane 6.16', 26.26',
56. '56'...Metal electrode7.27.57...Molecular element integrated circuit device8.
28.58...Molecular functional element 9.1.9',
29.29', 59.59'...Molecular electrode 0......
More than insulation film

Claims (1)

【特許請求の範囲】[Claims]  半導体集積回路装置表面の限定された領域に分子素子
集積回路が形成されて成り、該分子素子集積回路のポリ
アセチレン等から成る分子電極と、前記半導体集積回路
装置に形成された金属電極とが結線されて成る事を特徴
とする半導体集積回路装置。
A molecular element integrated circuit is formed in a limited area on the surface of a semiconductor integrated circuit device, and a molecular electrode made of polyacetylene or the like of the molecular element integrated circuit is connected to a metal electrode formed on the semiconductor integrated circuit device. A semiconductor integrated circuit device characterized by comprising:
JP1325026A 1989-12-15 1989-12-15 Semiconductor integrated circuit device Pending JPH03185869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1325026A JPH03185869A (en) 1989-12-15 1989-12-15 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1325026A JPH03185869A (en) 1989-12-15 1989-12-15 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH03185869A true JPH03185869A (en) 1991-08-13

Family

ID=18172317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1325026A Pending JPH03185869A (en) 1989-12-15 1989-12-15 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH03185869A (en)

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