JPH03185874A - Manufacture of thin film semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a thin film semiconductor device.

[Conventional technology] In recent years, insulating amorphous substrates such as glass and quartz have been used to realize large, high-resolution active matrix liquid crystal display panels, high-speed and high-resolution contact image sensors, three-dimensional ICs, etc. Attempts have been made to form high-performance semiconductor elements on insulating amorphous layers such as 5i02 and 5i02. In particular, in large liquid crystal display panels and the like, in order to meet the demand for low cost, it is becoming essential to form thin film transistors (TPT) on inexpensive low melting point glass substrates. Conventionally, for example, Journal of Applied
Physics Vol, 65(10) p, 3951
(1989), amorphous 5i(a-3
i), 5solid 5tate Elec
tronics '1101.32 (5) p, 39
1 (1989), IEEE Electron De
vice Letters Vol, 10 (3) p.
123 (1989), IEEE Transacti.
ons on Elec-tron Devices,
Vol, 36 (3) p, 529 (19B9)
As seen in et al., polycrystalline Si (poly-3i)
There are some that use

[Problem to be solved by the invention] However, when the active layer of TPT is made of a-3i, a-
Since the field effect mobility in 3i is small, the performance is extremely insufficient when considering the application to high-definition TV (HDT), which has recently been actively developed. To solve this problem, the active layer of TPT is made of polycrystalline Si film formed by low pressure chemical vapor deposition (LPGVD) instead of a-3i, or a-3i.
There has been an attempt to improve the performance of TFTs by manufacturing poly-Si whose grain size has been increased by annealing and solid-phase growth of i. Conventionally, the solid phase growth method has generally been to anneal an amorphous semiconductor thin film at a temperature of about 600° C. to grow crystals. However, even if annealed for a long time at a temperature of about 600° C., amorphous components remain at the grain boundaries, making it impossible to obtain a good crystalline thin film. For this reason, conventionally, in order to completely change this amorphous component to crystalline, it was necessary to conduct a process at a temperature of 1000°C or higher for 30 min.
, and had been annealed again. However, when such an annealing method is adopted, many trap levels exist in the resulting crystal grain boundaries, the grain boundary barrier hydride is high, and the field effect mobility of carriers in the crystal is reduced, resulting in TP.
The performance of T does not improve. Therefore, there has been an attempt to improve the performance of TPT by immersing it in H2 plasma for the purpose of terminating the trap levels in the grain boundaries. However, when H2 plasma is applied to a TPT on an insulating substrate, a problem frequently arises in that charge-up occurs and the TPT is destroyed.

Further, since long-time high-temperature annealing is required, there are problems such as the inability to use a low-cost, low-melting-point glass substrate.

The present invention solves the above problems, and its purpose is to form a high quality crystalline semiconductor thin film on an insulating substrate, and to
An object of the present invention is to provide a method for manufacturing TPT that does not require an unstable process such as the H2 plasma process that was conventionally required.

[Means for Solving the Problems] A method for manufacturing a thin film semiconductor device of the present invention includes a step of depositing an amorphous semiconductor on an insulating amorphous substrate, and a step of depositing the amorphous semiconductor at a temperature of 500 to 700°C. A first annealing step of annealing for 5 minutes to 90 hours, and after the first annealing step,
The method is characterized in that it includes at least a second annealing step in which the temperature is raised to a predetermined temperature of 900° C. or more at a heating rate of 10° C./sec or more, and annealing is performed at the predetermined temperature for 1 second or more.

[Example] Hereinafter, a solid phase growth annealing method will be explained based on FIG. First, an insulating substrate 10 such as a quartz substrate or a glass substrate
An amorphous semiconductor 102 is formed on top of the amorphous semiconductor 102. In this example, amorphous silicon is used as an example of an amorphous semiconductor.
The same applies to amorphous Ge and amorphous SiGe.

Note that a Si substrate covered with SiO2 may be used as the substrate. If a quartz substrate or a Si substrate covered with SiO2 is used, it can withstand a high temperature process of 1200°C, but if a glass substrate is used, it is limited to a low temperature process of about 6007°C or less due to its low softening temperature. Ru. First, an amorphous silicon thin film 1 is deposited on an insulating substrate 101.
02 is deposited (Fig. 1(a)). It is desirable that the amorphous silicon thin film 102 be uniform, contain no minute crystallites, and have no crystal growth nuclei at all. In the case of low pressure chemical vapor deposition (LPGVD), conditions in which the devoting temperature is as low as possible and the devoting speed is fast are suitable. LPGV
When using silane gas (SiH4) in D, the temperature is 500℃~
Decomposition and deposition is possible at a debo temperature of about 560°C, or about 300°C to 500°C when disilane gas (Si2He) is used. Trisilane gas (SisHs) has an even lower decomposition temperature. If the devoting temperature is increased, the deposited film becomes polycrystalline, so there is also a method of temporarily making it amorphous by implanting Si ions. Plasma chemical vapor deposition (PCVD)
In this case, the film can be formed even if the substrate temperature is 500°C or less.

In this example, the PCVD method was used, and the film forming gas was SiH4.
A mixed gas of 10% H2 and 90% H2 was used. The substrate temperature is 1
The temperature is 50 to 240°C, preferably 180°C. The internal pressure of the mixed gas is 0.8 Torr, rf power = 63 mW/
cm2, rf frequency = 13.56 MHz was used.

PCVD has the advantage that if hydrogen plasma or argon plasma treatment is performed immediately before deposition, cleaning of the substrate surface and film formation can be performed continuously. The photo-excited CVD method is also effective in that low-temperature deposition at 500° C. or lower, cleaning of the substrate surface, and film formation can be performed continuously.

In the case of high vacuum evaporation methods such as electron beam evaporation, since the film is porous, oxygen from the atmosphere is easily incorporated into the film, which hinders crystal growth. To prevent this,
It is effective to densify the film by performing low-temperature heat treatment at about 300° C. to 500° C. before in-phase growth annealing. The sputtering method is similar to the high vacuum evaporation method.

The poly-3i thin film produced as described above is subjected to an annealing process for solid phase growth of the thin film. As a solid phase growth method, furnace annealing using a quartz tube is convenient. As the annealing atmosphere, nitrogen gas, hydrogen gas, argon gas, helium gas, etc. are used. 1×10-a to lXl
Annealing may be performed in a high vacuum atmosphere of 0-'θTorr. In-phase growth annealing temperature is approximately 500 °C ~ 7
00°C, and annealing is preferably performed at about 600°C for about 5 to 20 hours. In low-temperature annealing, only crystal grains with crystal orientations with low activation energy for crystal growth grow selectively and slowly, forming large-grain polycrystalline silicon 103 with a grain size of approximately 1 μm (Figure 1 (b)). . Microscopically, amorphous regions 104 remain at the grain boundaries of the poly-3i thin film produced in this manner. In Figure 1 (b),
This amorphous region 104 is exaggerated. The amorphous region 104 at the grain boundary cannot be completely transformed into a crystalline state even if the solid phase growth annealing time is increased.

For this reason, conventionally, it has been necessary to transform the amorphous region 104 into a crystalline state by performing high temperature treatment at 1000° C. at this stage or during the gate oxide film manufacturing process during TPT manufacturing. However, when such an annealing method is adopted, the density of trap levels in the resulting crystal grain boundaries is approximately 1.2xlO12cm-2, and the field-effect mobility of carriers in the crystal is at most 50cm in the case of an n-channel.
It did not exceed 2/V-s. Therefore, hydrogen ions are introduced using methods such as H2 plasma method, hydrogen ion implantation method, or hydrogen diffusion method from plasma nitride film to terminate dangling bonds and defect levels at grain boundaries, etc.
There are also attempts to improve the performance of However, ionized plasma,
When ions or the like are exposed to a TPT on an insulating substrate, a problem frequently arises in that charge-up occurs and the TPT is destroyed. In addition, when the gate electrode is made of n-type poly-3i, the hydrogenated non-doped poly-3i exhibits properties closer to n-type, so the threshold voltage V of TPT is about 1 V, especially in the case of n-channel TPT. There was a problem with the shift to This characteristic shift problem appears as an increase in the OFF current in the n-channel TPT. Conventionally, to solve this problem, TPT channel poly
A method of doping poly-3i with a small amount of boron, a so-called channel doping method, has been used to make poly-3i closer to the p-type. However, when channel doping is performed by ion implantation, it is difficult to control the amount of doping, and the number of steps increases by one step, making the process more complicated.

Therefore, in this example, rapid thermal annealing (RT
A) was applied to a poly-3il film. That is, a temperature change as shown in the curve in FIG. 3 was applied to the poly-Si thin film. The temperature increase rate should be less than 5-b, and the annealing time during temperature increase should be 1 sec or more, but it is desirable to provide a temperature cycle like the curve shown in Figure 3.
After RTA, the amorphous region 104 completely transforms into crystalline, and new grain boundaries 105 are formed (Fig. 1 (C)).
. The poly-3i thin film produced by this method has a low trap density at grain boundaries of 6.2×10'ICm-2, a small grain boundary barrier hide, and a large grain size po 1 with an average grain size of 1 μm or more. It has the characteristic of being a y-3i thin film. The TPT produced in this way was n
In case of channel, field effect mobility is 150cm27V-s
Until. Therefore, using this poly-3i, TP
If T is manufactured, a hydrogenation process such as an H2 plasma process, which was conventionally necessary, becomes unnecessary. Accordingly, a great advantage arises in that channel doping of the n-channel TPT can also be omitted.

The large grain polycrystalline silicon thin film produced using the present invention is
An example of application to a thin film transistor will be explained with reference to FIG. A large-grain polycrystalline silicon thin film substrate obtained by solid-phase growth is shown in FIG. 2(a). 201 is an insulating substrate. 202 is a large grain polycrystalline silicon thin film formed by solid phase growth. 203 indicates a grain boundary.

Next, the silicon thin film is patterned by photolithography to form an island shape as shown in FIG. 2(b) to form a channel region. Next, as shown in Figure 2(c),
A gate insulating film 204 is formed so that the gate insulating film 204 is formed. The gate insulating film can be formed by LPCVD, photo-excited CVD, plasma CVD, ECR plasma CVD, high vacuum evaporation, plasma oxidation, or high pressure oxidation at temperatures below 500°C. There is a low temperature method. The gate insulating film formed by the low-temperature method becomes an excellent film that is denser and has fewer interface states by heat treatment. When using a quartz substrate as the amorphous insulating substrate 201, a thermal oxidation method can be used. The thermal oxidation method includes a dry oxidation method and a wet oxidation method.
Although the oxidation temperature is as high as 1000° C. or more, the dry oxidation method is more suitable because the film quality is excellent.

Next, as shown in FIG. 2(d), the gate electrode 205
form. The gate electrode material is poly-3i
, or molybdenum silicide, or metal films such as aluminum or chromium, or ITO or 5
A transparent conductive film such as n02 can be used. Film forming methods include CVD, sputtering, vacuum evaporation, and the like, but detailed description thereof will be omitted here. When using poly-3i for the gate electrode,
The present invention can be applied as is. That is, a doped amorphous semiconductor thin film is grown in a solid phase to obtain a large grain size p.

By performing RTA after producing the 1y-3i thin film, it is possible to improve the quality and lower the resistance of the gate electrode.

Subsequently, as shown in FIG. 2(e), the gate electrode 20
Impurity ions are implanted using No. 5 as a mask to form a source region 206 and a drain region 207 in a self-aligned manner. As the impurity, P''' or AS' is used when manufacturing an Nch transistor, and Bo, etc. is used when manufacturing a Pch transistor. In addition to the ion implantation method, laser doping can be used as the impurity addition method. Alternatively, there are methods such as plasma doping.208
The arrow shown by indicates the impurity ion beam.

When a quartz substrate is used as the amorphous insulating substrate 201, a thermal diffusion method can be used for doping. The impurity degree is approximately 1 x 1015 to 1 x 10''Cm-'.

Subsequently, as shown in FIG. 2(f), an interlayer insulating film 20 is formed.
Layer 9. As the interlayer insulating film material, an oxide film, a nitride film, or the like is used. The film thickness may be any thickness as long as the insulation is good, but it is usually from several thousand to several micrometers.

A simple method for forming the nitride film is the LPCVD method or the plasma CVD method. For the reaction, a mixed gas of ammonia gas (NH3), silane gas, and nitrogen gas,
Alternatively, a mixed gas of silane gas and nitrogen gas is used.

Next, as shown in FIG. 2(g), contact holes are formed in the interlayer insulating film and the gate insulating film, contact electrodes are formed, and a source electrode 210 and a drain electrode 211 are formed.
shall be. The source electrode and drain electrode are formed of a metal material such as aluminum, and the TPT is completed.

[Effects of the Invention] When a thin film transistor is made using the large-grain polycrystalline silicon thin film obtained by the present invention, excellent characteristics can be obtained. Compared to the conventional art, the ON current of the thin film transistor increases and the OFF current decreases. Furthermore, the threshold voltage is also reduced, and transistor characteristics are greatly improved.

'Since it is possible to fabricate thin film transistors with excellent characteristics on an amorphous insulating substrate, sufficient high-speed operation can be achieved even when applied to an active matrix substrate where a driver circuit is integrated on the same substrate. Furthermore, it has great effects on reducing power supply voltage, reducing current consumption, and improving reliability. In addition, since it is possible to manufacture by a low-temperature process at 600° C. or lower, this is highly effective in reducing the cost and increasing the area of active matrix substrates.

When the present invention is applied to a contact image sensor in which a photoelectric conversion element and its scanning circuit are integrated on the same chip, it is possible to increase the reading speed, increase the resolution, and increase the gradation. produce an effect. Once high resolution is achieved, it will be easier to apply it to a contact type image sensor for color reading. Of course, this has great effects in reducing power supply voltage, reducing current consumption, and improving reliability.

Also, since it can be produced by a low-temperature process,
Close-contact image sensor chip can be made longer,
- A reading device for large facsimile machines such as A4 size or A3 size can be realized using a book chip. Therefore, it is possible to avoid techniques that require a lot of man-hours and have poor reliability, such as the process of joining two sensor chips together, and the mounting yield can also be improved.

In addition to quartz and glass substrates, sapphire substrates (
A1203) or MgO・A12Ch.

Crystalline insulating substrates such as B P and Ca F 2 can also be used.

Although the description has been given above using a thin film transistor as an example, the present invention can also be applied to elements using thin films such as bipolar transistors or heterojunction bipolar transistors. In addition, SO such as a three-dimensional device
The present invention can also be applied to elements using I technology.

[Brief explanation of drawings]

FIG. 1 is a process diagram of solid phase growth annealing of the present invention. FIG. 2 is a manufacturing process diagram in which the method for manufacturing a thin film semiconductor device of the present invention is applied to a thin film transistor. FIG. 3 is a diagram showing an example of the temperature cycle of the RTA process. 101.201...Insulating substrate 102...
・・・・・・Amorphous semiconductor 103.202・・・・・・
...Large grain size polycrystalline silicon 104...
・Amorphous region O5, 203... Grain boundary 04...
...Gate insulating film 05...Gate electrode 06...Source region 07...Drain region 08... ...Ion beam 09...Interlayer insulating film 10...Source electrode 11...Drain electrode or higher

Claims (1)

[Claims] A step of depositing an amorphous semiconductor on an insulating amorphous substrate, a first annealing step of annealing the amorphous semiconductor at a temperature of 500 to 700° C. for 5 minutes to 90 hours, and after the first annealing step. , 900℃ at a heating rate of 10℃/sec or more
A method for manufacturing a thin film semiconductor device, comprising at least a second annealing step of raising the temperature to the above predetermined temperature and annealing at the predetermined temperature for 1 second or more.