JPH03185876A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03185876A JPH03185876A JP1325024A JP32502489A JPH03185876A JP H03185876 A JPH03185876 A JP H03185876A JP 1325024 A JP1325024 A JP 1325024A JP 32502489 A JP32502489 A JP 32502489A JP H03185876 A JPH03185876 A JP H03185876A
- Authority
- JP
- Japan
- Prior art keywords
- film
- amorphous
- schottky junction
- insulating film
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は新しい樋造の′＃を気的誓き込み型の読み出し
専用記憶装置（ＥＰＲＯＭ）に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a new Hizo's programmable read-only memory (EPROM).
［従来の技術］
従来、Ｐ−Ｎ接合上にアモルファス・シリコン膜を形成
し、該アモルファス・シリコン膜上に電極を形成したＥ
ＰＲＯＭはあった。[Prior art] Conventionally, an amorphous silicon film is formed on a P-N junction, and an electrode is formed on the amorphous silicon film.
There was a PROM.
［発明が解決しようとする課題］
しかし、上記従来技術によると、ＥＰＲＯＭの読み出し
速度が遅いと云う課題があった。[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has a problem in that the reading speed of the EPROM is slow.
本発明は、かかる従来技術の課題を解決し、高速読み出
しが可能な新しいＥＦＲＯＭ半導体装置構造を提供する
事を目的とする。It is an object of the present invention to solve the problems of the prior art and to provide a new EFROM semiconductor device structure capable of high-speed reading.
［課題を解決するための手段］
上記課題を解決するために、本発明は、ＫＰＲ９Ｍ半導
体装置に関し、従来Ｐ−Ｎ接合上にアモルファス・シリ
コン膜ヲ形成するのに対し、ショットキー接合上にアモ
ルファス・シリコン膜す形成する手段をとる事を基本と
する。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a KPR9M semiconductor device, in which an amorphous silicon film is formed on a Schottky junction, whereas conventionally an amorphous silicon film is formed on a P-N junction.・The basic method is to form a silicon film.
［実施例］ 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図、２ｇ２図及び第５図は、本発明の実施例な示す
、ＥＰＲＯＭの要部の断面図である。FIGS. 1, 2g2, and 5 are cross-sectional views of essential parts of an EPROM, which is an embodiment of the present invention.
第１図では、サファイア基板１１０表面に３１単結晶膜
１２が形成され、更に、絶縁膜１３が形成され、該絶縁
膜１５に開けられた窓部にｐｔＳｉ等から成るショット
キー接合１４を形成し、該ショットキー接合１４の上に
アモルファスＳｉ［１６を形成し、該アモルファス５ｉ
ｌＪ１６の上にＡｔやＴｉ、ＴｉＮ等から戒る電極１６
′？：形成したものである。In FIG. 1, a single crystal film 12 is formed on the surface of a sapphire substrate 110, an insulating film 13 is further formed, and a Schottky junction 14 made of ptSi or the like is formed in a window formed in the insulating film 15. , amorphous Si[16 is formed on the Schottky junction 14, and the amorphous Si[16]
Electrode 16 that is protected from At, Ti, TiN, etc. on lJ16
′? : It was formed.
第２図では、Ｓｉ単結晶基板２１０表面に、拡＃１１．
層２２及び絶縁膜２３を形成し、前記拡散層２２上の前
記絶縁膜２３に設けられた窓部に、ショットキー接合２
４を形威し、該ショットキー接合２４上にアモルファス
Ｓｉ膜２５を形成し、該アモルファスＳ１膜２５上に電
極２６χ形成したものである。In FIG. 2, #11.
A layer 22 and an insulating film 23 are formed, and a Schottky junction 2 is formed in a window provided in the insulating film 23 on the diffusion layer 22.
4, an amorphous Si film 25 is formed on the Schottky junction 24, and an electrode 26χ is formed on the amorphous S1 film 25.
第５図では、Ｓｉ単結晶基板３１上に、第１の絶縁膜５
２な形成し、該第１の絶縁膜５２に開けられた窓部を含
む表面に、エピタキシャル処理により窓部に単結晶Ｓｉ
エピタキシャル膜５５とそれに連もなった多結晶Ｓ１膜
５４を形成し、その上に第２の絶縁膜５５な形成し、該
第２の絶縁膜３５の前記単結晶エピタキシャル膜５５上
に開けられた窓部上にショットキー接合３６及びアモル
ファスＳｉ膜３７を形成し、該アモルファスＳｉ膜上に
電極５Ｂを形成したものである。尚、第１の絶縁膜５２
上の多結晶Ｓｉｌ［５４ｆｔ：単結晶化した上にショッ
トキー接合とアモルファスＳｉ膜形成を行ない、該アモ
ルファスＳ１膜上に電極な形成しても良いことは云うま
でもない。In FIG. 5, a first insulating film 5 is formed on a Si single crystal substrate 31.
2 is formed, and single crystal Si is formed in the window portion by epitaxial treatment on the surface including the window portion opened in the first insulating film 52.
An epitaxial film 55 and a polycrystalline S1 film 54 connected thereto are formed, a second insulating film 55 is formed thereon, and an opening is formed on the single crystal epitaxial film 55 of the second insulating film 35. A Schottky junction 36 and an amorphous Si film 37 are formed on the window portion, and an electrode 5B is formed on the amorphous Si film. Note that the first insulating film 52
Needless to say, it is also possible to form a Schottky junction and an amorphous Si film on the polycrystalline Sil [54ft: single crystallized film] and form an electrode on the amorphous S1 film.
［発明の効果コ
本発明により、高速読み出しが可能なりＦＲＯＭを製作
することができる効果がある。[Effects of the Invention] The present invention has the advantage that high-speed reading is possible and FROM can be manufactured.
第１図、第２図及び第３図は、本発明の実施例を示すｌ
ＰＲＯＭの要部の断面図である。
１．１・・・・・・・・・す７アイヤ基板１２・・・・
・・・・・Ｓ１単結晶膜
３．２５・・・・・・絶縁膜
４．２４．５６・・・・・・ショットキー接合５．２５
．５７・・・・・・アモルファスｓ１［６，２６，５８
・・・・・・電 極
１．３１・・・・・・ｓ１単結晶基板
２・・・・・・・・・・・・・・・拡散層２・・・・・
・・・・・・・・・・第１の絶縁膜５・・・・・・・・
・・・・・・・単結晶Ｓｉエピタキシャル膜４・・・・
・・・・・・・・・・・多結晶Ｓｉ膜５・・・・・・・
・・・・・・・・第２の絶縁膜以上1, 2 and 3 show embodiments of the present invention.
FIG. 3 is a cross-sectional view of the main parts of PROM. 1.1...7 Ayer board 12...
...S1 single crystal film 3.25 ...Insulating film 4.24.56 ...Schottky junction 5.25
．． 57...Amorphous s1[6,26,58
......Electrode 1.31...s1 Single crystal substrate 2...Diffusion layer 2...
......First insulating film 5...
......Single crystal Si epitaxial film 4...
......Polycrystalline Si film 5...
・・・・・・Second insulating film or higher
Claims (1)
ー接合が形成されると共に、該ショットキー接合部上に
はアモルファス・シリコン膜が形成され、該アモルファ
ス・シリコン膜上には電極が形成されて成る事を特徴と
する電気的書き込み形読み出し専用の記憶装置となる半
導体装置。A Schottky junction is formed on the semiconductor single crystal substrate or the semiconductor single crystal film, an amorphous silicon film is formed on the Schottky junction, and an electrode is formed on the amorphous silicon film. What is claimed is: 1. A semiconductor device that serves as an electrically written read-only storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1325024A JPH03185876A (en) | 1989-12-15 | 1989-12-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1325024A JPH03185876A (en) | 1989-12-15 | 1989-12-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03185876A true JPH03185876A (en) | 1991-08-13 |
Family
ID=18172292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1325024A Pending JPH03185876A (en) | 1989-12-15 | 1989-12-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03185876A (en) |
-
1989
- 1989-12-15 JP JP1325024A patent/JPH03185876A/en active Pending
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