JPH03185897A - Multilayer wiring board manufacturing method - Google Patents
Multilayer wiring board manufacturing methodInfo
- Publication number
- JPH03185897A JPH03185897A JP1326320A JP32632089A JPH03185897A JP H03185897 A JPH03185897 A JP H03185897A JP 1326320 A JP1326320 A JP 1326320A JP 32632089 A JP32632089 A JP 32632089A JP H03185897 A JPH03185897 A JP H03185897A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- common electrode
- connection electrodes
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Electrical Connectors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電気機器等に使用される多層配線基板における
配線基板上に形成される接続電極のめっきの方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of plating connection electrodes formed on a wiring board in a multilayer wiring board used in electrical equipment and the like.
従来の技術
近年、電子機器の小型化に伴い高密度な回路基板が要求
されるようになってきた。従来の回路基板の電極は、プ
リント基板ではCu 、セラミック基板ではCu、Ag
7Pd、Ag−Pt等が多く使用されているが、高密度
な回路基板を得るためにICのペアチップを搭載しよう
とすると、回路基板のICとの接続電極部に金めつき等
の処理を施す必要があり、したがってこれ1では回路基
板を無電解金めっき液に浸して金めつきを施していた。BACKGROUND OF THE INVENTION In recent years, with the miniaturization of electronic devices, high-density circuit boards have been required. Conventional circuit board electrodes are Cu for printed circuit boards and Cu and Ag for ceramic boards.
7Pd, Ag-Pt, etc. are often used, but when trying to mount a pair of IC chips in order to obtain a high-density circuit board, it is necessary to apply treatments such as gold plating to the electrodes connected to the IC on the circuit board. Therefore, in this first method, gold plating was performed by dipping the circuit board in an electroless gold plating solution.
発明が解決しようとする課題
しかしながら上記のようなめっき方法では、表面に露出
した電極部全体に金が析出してしまい、コストが高くつ
いてしまう欠点があった。筐た。Problems to be Solved by the Invention However, the above-mentioned plating method has the disadvantage that gold is deposited on the entire electrode portion exposed on the surface, resulting in high costs. It was a cabinet.
レジスト等によりめっきの不必要部に予じめマスキング
処理を行った場合、一般に無電解めっき液は強アルカリ
であるためレジストが侵されてしまい、不必要な部分に
まで金が析出してしまうことがあった。さらに、レジス
トの耐薬品性という面からみると電気めっき液のpHは
中性に近く、電気めっきを行うのであればレジストは十
分使用に耐えるが、電気めっきをしようとすると、電気
めっき時に電気めっきされる複数の各電極部にそれぞれ
所定の電圧を印加する必要があり、現実問題としては不
可能に近いものであった。If masking is performed in advance on areas where plating is not needed using a resist, etc., the resist will be eroded because the electroless plating solution is generally a strong alkali, resulting in gold being deposited on unnecessary areas. was there. Furthermore, in terms of the chemical resistance of the resist, the pH of the electroplating solution is close to neutral, and the resist can withstand use sufficiently if electroplating is performed. It is necessary to apply a predetermined voltage to each of the plurality of electrode parts, which is almost impossible in practice.
本発明はこのような点に対応して、多層配線基板の表面
に形成された所定の電極に電気めっきを行う製造方法を
提供することを目的とする。In response to these points, it is an object of the present invention to provide a manufacturing method for electroplating predetermined electrodes formed on the surface of a multilayer wiring board.
課題を解決するための手段
本発明の多層配線基板の製造方法は、製品となる第1の
多層配線基板部と一体的に連続した第2の多層配線基板
部上に形解された共通電極に、第1の多層配線基板面の
めっきすべき複数の接続電極を第1の多層配線基板部内
の内層導体を介して接続し、Wetめっき時に前記共通
電極に所定の電圧を印加して前記複数の接続電極にそれ
ぞれ電気めっき層を形成し、そのめっき形成後に前記第
1と第2の多層配線基板部を切離し、前記接続IFIL
極に内層導体を介して電気的に接続されていた前記各接
続電極を相互に電気的に切離すことを特徴とするもので
ある。Means for Solving the Problems The method for manufacturing a multilayer wiring board of the present invention includes a common electrode formed on a second multilayer wiring board part that is integrally continuous with a first multilayer wiring board part that is a product. , a plurality of connection electrodes to be plated on the surface of the first multilayer wiring board are connected via an inner layer conductor in the first multilayer wiring board section, and a predetermined voltage is applied to the common electrode during wet plating to connect the plurality of connection electrodes to be plated. An electroplating layer is formed on each of the connection electrodes, and after the plating is formed, the first and second multilayer wiring board parts are separated, and the connection IFIL is separated from the first and second multilayer wiring board parts.
The method is characterized in that the connection electrodes that are electrically connected to the poles via the inner layer conductors are electrically separated from each other.
作 用
上述の方法によれば、電気めっきすべき複数の接続!極
は、あらかじめ多層配線基板の内部に形成された内層導
体を介して共通電極に接続されているため、めっき時に
この共通電極に所定の電圧を印加すれば複数の接続電極
にそれぞれ所定の電圧を印加できるものである。また、
多層配線基板の内部の内層導体を使用するため、前記接
続電極と共通電極とを接続するための導電パターンの設
計の自由度も高くなるものである。According to the method described above, multiple connections to be electroplated! The poles are connected to a common electrode via an inner layer conductor formed inside the multilayer wiring board in advance, so if a predetermined voltage is applied to this common electrode during plating, a predetermined voltage is applied to each of the multiple connection electrodes. It can be applied. Also,
Since the inner layer conductor inside the multilayer wiring board is used, the degree of freedom in designing the conductive pattern for connecting the connection electrode and the common electrode is increased.
実施例
以下、本発明の一実施例の多層配線基板の製造方法につ
いて1図面を参照しながら説明する。第2図に示すよう
に、筐ずガラスセラミックを有機バインダー中に均一分
散したグリーンシート7a。EXAMPLE Hereinafter, a method for manufacturing a multilayer wiring board according to an example of the present invention will be described with reference to one drawing. As shown in FIG. 2, a green sheet 7a is a green sheet 7a in which a glass ceramic is uniformly dispersed in an organic binder.
7b 、7cに、NCパンチングによってそれぞれピア
ホールを明けた後、酸化銅ペースト5をそのピアホール
に充填し、同じく酸化鋼ペースト5にてグリーンシー)
7b 、7cの表面に配線パターン6を印刷乾燥したも
のを複数枚積層し、約500℃の空気中で焼成すること
により前記有機バインダーを散逸させたのち、約360
℃の窒素と水素の混合ガス中で酸化銅を銅に還元し、さ
らに900℃の窒素中で銅とガラスセラミックを焼結さ
せ。After making a pier hole in 7b and 7c by NC punching, the pier hole was filled with copper oxide paste 5, and green sea was filled with oxidized steel paste 5).
A plurality of printed and dried wiring patterns 6 are laminated on the surfaces of 7b and 7c, and fired in air at about 500°C to dissipate the organic binder.
Copper oxide was reduced to copper in a mixed gas of nitrogen and hydrogen at 900°C, and the copper and glass ceramic were sintered in nitrogen at 900°C.
多層配線基板を形成する。このとき、グリーンシー)
7 aにはあらかじめスリット3を設けて釦き、製品と
なる第1の多層配線基板部1aと、めっき後に除去され
る第2の多層配線基板部1bとに分離しやすいようにし
ておく。また、配線パターン6の設計は、第1図に示す
ように第1の多層配線基板部1aの表面層には、めっき
される、複数の電fM2bとめっきされない電極2aが
形成され。Form a multilayer wiring board. At this time, Green Sea)
A slit 3 is provided in advance in 7a to facilitate separation into the first multilayer wiring board part 1a, which will become a product, and the second multilayer wiring board part 1b, which will be removed after plating. Further, the design of the wiring pattern 6 is such that, as shown in FIG. 1, a plurality of plated electrodes fM2b and an unplated electrode 2a are formed on the surface layer of the first multilayer wiring board portion 1a.
第2の多層配線基板部1bの表面層には共通電極2Cが
形成されるように構成され、また第2図に示すようにめ
っきされる電極2bと共通電極2aは多層配線基板内の
内層導体4によって接続されている。次に、この多層配
線基板を金めつき液に浸漬し、共通電極2Cを電源の負
電極に接続し、白金を電源の正電極に接続し、0.04
mA/dの電流密度でF110分間電気めっきを行い、
めっきされる電極2bの表面のみ選択的に金めつきを約
3μm析出させる。最後に、スリット3の部分で、第1
の多層配線基板部1aと第2の多層配線基板部1bを分
割し、共通電極2cを介して電気的に接続されていた複
数の電極2bを電気的に分離することによシ目的とする
多層配線基板を得る。なお、上記の製造工程における材
料や数値は一例であり、目的を達する範囲で変更しても
差支えない。A common electrode 2C is formed on the surface layer of the second multilayer wiring board part 1b, and as shown in FIG. Connected by 4. Next, this multilayer wiring board is immersed in a gold plating solution, the common electrode 2C is connected to the negative electrode of the power source, and the platinum is connected to the positive electrode of the power source.
Electroplating was performed for F110 minutes at a current density of mA/d,
Gold plating is selectively deposited to a thickness of about 3 μm only on the surface of the electrode 2b to be plated. Finally, at the slit 3 part,
The multilayer wiring board section 1a and the second multilayer wiring board section 1b are divided, and the plurality of electrodes 2b that are electrically connected via the common electrode 2c are electrically separated. Obtain a wiring board. Note that the materials and numerical values in the above manufacturing process are merely examples, and may be changed within the range that achieves the purpose.
発明の効果
以上のように本発明によれば、製品となる第1の多層配
線基板部の表面に形成された複数の接続電極を、それぞ
れ前記第1の多層配線基板部と一体的に連続させて形成
された第2の多層配線基板上の共通電極に、前記第1の
多層配線基板部内の内層導体を介して接続し、前記接続
電極に電気めっき層を形成した後、前記第1と第2の多
層配線基板部を切離すことにより、選択的に部分電気め
っきが可能になシ、マスキング工程の必要がないなど、
工程の簡素化が図れるも、のである。Effects of the Invention As described above, according to the present invention, a plurality of connection electrodes formed on the surface of a first multilayer wiring board part, which is a product, are each integrally continuous with the first multilayer wiring board part. After forming an electroplating layer on the connection electrode, the common electrode is connected to the common electrode on the second multilayer wiring board formed by using the inner layer conductor in the first multilayer wiring board section. By separating the multilayer wiring board part 2, selective electroplating becomes possible, and there is no need for a masking process.
Although it is possible to simplify the process, it is also possible.
第1図は本発明の多層配線基板の製造方法の一実施例に
おける電気めっき前の状態の多層配線基板を示す斜視図
、第2図は同実施例の焼成前の状態の多層配線基板の側
断面図である。
1a・・・・・・第1の多層配線基板、1b・・・・・
・第2の多層配線基板、2a・・・・・・めっきされな
い電極、2b・・・・・・めっきされる電極、2C・・
・・・・共通電極、3・・・・・・スリット、4・・・
・・・内部導体。FIG. 1 is a perspective view showing a multilayer wiring board before electroplating in one embodiment of the method for manufacturing a multilayer wiring board of the present invention, and FIG. 2 is a side view of the multilayer wiring board in a state before firing in the same embodiment. FIG. 1a...first multilayer wiring board, 1b...
・Second multilayer wiring board, 2a...electrode not plated, 2b...electrode to be plated, 2C...
...Common electrode, 3...Slit, 4...
...Inner conductor.
Claims (1)
電極を前記第1の多層配線基板部内の内層導体を介して
前記第1の多層配線基板部と一体的に連続した第2の多
層配線基板部の共通電極に接続し、前記共通電極を用い
て前記複数の接続電極に電気めっき層を形成し、その電
気めっき層形成後に前記第1と第2の多層配線基板部を
切り離し、前記共通電極内層導体を介して電気的に接続
されていた前記複数の接続電極を相互に電気的に切離す
多層配線基板の製造方法。A plurality of connection electrodes formed on the surface of the first multilayer wiring board section are connected to a second multilayer interconnection board integrally connected to the first multilayer wiring board section via inner layer conductors in the first multilayer wiring board section. connecting to a common electrode of a wiring board part, forming an electroplating layer on the plurality of connection electrodes using the common electrode, separating the first and second multilayer wiring board parts after forming the electroplating layer, and A method for manufacturing a multilayer wiring board, in which the plurality of connection electrodes that are electrically connected via a common electrode inner layer conductor are electrically separated from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1326320A JPH03185897A (en) | 1989-12-15 | 1989-12-15 | Multilayer wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1326320A JPH03185897A (en) | 1989-12-15 | 1989-12-15 | Multilayer wiring board manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03185897A true JPH03185897A (en) | 1991-08-13 |
Family
ID=18186451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1326320A Pending JPH03185897A (en) | 1989-12-15 | 1989-12-15 | Multilayer wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03185897A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2742452A1 (en) * | 1995-12-18 | 1997-06-20 | Commissariat Energie Atomique | SUPPORT FOR ELECTROCHEMICAL DEPOSIT |
-
1989
- 1989-12-15 JP JP1326320A patent/JPH03185897A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2742452A1 (en) * | 1995-12-18 | 1997-06-20 | Commissariat Energie Atomique | SUPPORT FOR ELECTROCHEMICAL DEPOSIT |
| EP0780890A1 (en) * | 1995-12-18 | 1997-06-25 | Commissariat A L'energie Atomique | Support for electrochemical deposition |
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