JPH03185917A - Data bus circuit - Google Patents

Abstract

PURPOSE:To prevent a delay in signal transmission and to reduce power consumption by providing a couple of data buses, plural bipolar transistors(TRs), MOS TRs and resistors, and causing a minute signal amplitude on the data buses. CONSTITUTION:A couple of data buses are provided, which consists of a 1st data bus 1 whose level is fixed and a 2nd data bus 2 whose level is fluctuated in response to a signal. Moreover, 1st and 2nd MOS TRs Q1, Q5 are connected to the buses 1, 2 via 1st and 2nd resistors R1, R2 and 1st and 2nd bipolar TRs Q2, Q6. Then the product of the resistance of the resistor R1 and the channel width of the TR Q1 is made equal to one-half the product of the resistance of the resistor R2 and the channel width of the TR Q6. Thus, the long data buses with a large wiring capacitance are driven stable at a high speed when with the bipolar TRs by utilizing a current ratio and a ratio of load resistors of the MOS TRs whose drain voltage is almost fixed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to data bus circuits, and in particular, to data bus circuits that are ideal for ultra-LSIs that can drive data buses with long wiring lengths and large load capacities at high speed and with low power consumption. Regarding data bus circuits.

[Conventional technology]

As a conventional data bus circuit of this type, a CMO3 circuit having a tri-state output has been used.

[Problem to be solved by the invention]

In the conventional CMO3 circuit described above, the signal amplitude is usually as large as 5V, so the wiring capacitance is charged and discharged for a long data bus. This has the disadvantage that signal transmission is delayed and power consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data bus circuit in which the above-mentioned drawbacks are overcome, signal transmission is not delayed, and power consumption is reduced.

[Means to solve the problem]

The bottom of the data bus according to the present invention includes a pair of data buses, a first data bus having a fixed potential and a second data bus having a fluctuating potential. , the first M
An OS transistor is connected to the second data bus, and a second M
An OS transistor is connected, a fixed bias is applied to the base of the first bipolar transistor and the gate of the first MOS transistor, and a fixed bias is applied to the base of the second bipolar transistor and the gate of the second transistor. It is characterized in that a data bus selection signal or data signal is applied.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a data bus circuit according to an embodiment of the present invention.

In FIG. 1, the data bus circuit of this embodiment has a one-to-one
Load resistors R1, R2 and bipolar transistors Q2. Q, are connected to these bipolar transistors Q2. N-channel MO3 transistors Q, , Q5 are connected to the emitter of Q6, respectively. The gate of transistor Q1 is biased to the highest potential, and the input signal V1 is applied to the gate of transistor Q5. The base of transistor Q2 has a bias voltage V,
is applied, and a data bus selection signal v2 is applied to the base of the transistor Q6. It is also possible to input the input signal Vl and the selection signal V2 interchangeably. Resistors R1 and R2 are connected to a bias voltage V to determine the potential of the data bus.

Now, assuming that the channel width of transistor Q1 is Wl and the channel width of transistor Q is W5, and the channel lengths are equal, the drain voltages of transistors Q I and Q s are fixed and equal by bipolar transistors Q2 and Q6, so The current ratio of transistors Q+ and Qs is W+
/Ws. Input signal VI causes transistor Q
, becomes ○N/○FF, the potential of data bus 2 becomes,
In order to increase or decrease the potential of data bus 1 as the center, 2R,・W 2 = R2・W, ...
...The resistance values R1 and R2 and the channel widths W1 and W may be determined so as to satisfy (1).

Normally, it is sufficient to set [R1=R2] and (2WI=WS). However, since a steady current flows through the transistor Q1, power consumption increases when the number of data buses is large. In order to reduce power consumption, the steady current can be reduced by increasing the resistance value R3 and decreasing the width W1.

The amplitude of the data bus is equal to the product of the on-current of resistor R2 and transistor Q. In order to reduce the delay time with respect to the wiring capacitance, it is necessary to reduce the signal amplitude as much as the noise margin allows. In this embodiment, since the data buses are paired, it is resistant to common mode noise and it is possible to lower the signal amplitude.

In this way, this embodiment includes a pair of data buses consisting of the first data bus 1 whose potential is fixed and the second data bus 2 whose potential varies according to the signal. The data buses 1.2 and 2 have first and second resistors Rr and R2, respectively, and a first
The first and second MOS transistors Q+ and Qs are connected through the second bipolar transistor Q2 and Q6, and in particular, the product of the first resistance value R1 and the channel width of the first MOS transistor Q is It is characterized by being half the product of the second resistance value R2 and the channel width of the second MOS transistor Q6.

FIG. 2 is a circuit diagram showing a data bus circuit according to another embodiment of the present invention.

In FIG. 2, the data bus circuit of this embodiment has bipolar transistor pairs Qs, Q4 and resistors R, . Transistor Q1
are connected in series, and a bipolar transistor pair Q,
, Q, and a series body of MOS transistor Q5 are connected to data bus 2, and readout circuit 3 is connected to data bus 1.2.
It is connected to the.

The potential of the data bus 1.2 is given by the bipolar transistors 6, Q3, Qs and the bias voltage VB. A switch circuit is required to decide whether to put the input signal V1 on the data bus or not. For this purpose, a bipolar transistor Q7 is added. When the potential of the signal V2 applied to the base of the transistor Q6 is made higher than the potential V,l, the transistor Q6 becomes conductive, and the current of the transistor Q5 flows through the resistor R2 in response to the input signal V1, and is applied to the data bus 2. A signal appears. When voltage V2 becomes lower than V, transistor Q is cut off, the collector of transistor Q6 becomes high impedance, and transistors Qs and Qa are separated from data bus 2. If the above equation (1) is satisfied, the potential of data bus 2 is always
It will swing around the potential of .

Transistors Q6 to Q1 surrounded by broken lines. The circuit consisting of the following is the signal readout circuit 3. Transistor Q8 is a current source and selects whether or not to read based on signal V3. When the potential V3 becomes high level and the transistor Q8 turns on, the output signal V is applied to the collector of the transistor Q.
, appears. Bipolar transistor Q9. QIO is a pair of transistors and amplifies minute signal differences on data bus 1.2. These bipolar transistors Q
9゜Ql. Since the gain of the data bus 1.2 is high, several hundred mV is sufficient as the amplitude of the data bus 1.2.

Therefore, even if the data bus 1.2 is long and the wiring capacity is large, signals can be transmitted at high speed. The output amplitude of the output signal V is approximately determined by the dimensions of the transistors Q a and Q Io. Therefore, the potential of the output signal V, of the transistor Q,
It is easy to avoid saturation.

As described above, in the embodiment of the present invention, by connecting a bipolar transistor to a MOS transistor, the current change of the MOS transistor is converted into a minute signal amplitude, and the minute signal amplitude is transmitted through a pair of data buses. In order to stably generate minute signal amplitudes, a dimensional ratio of MOS transistors or resistors is used, and a pair of data buses is used to further increase resistance to noise.

〔Effect of the invention〕

As explained above, the present invention is particularly capable of generating a minute signal amplitude on a pair of data buses when using a bipolar transistor with a substantially fixed drain voltage of an M○S transistor using the ratio of current ratio and load resistance. This has the effect of making it possible to drive a long data bus with a large wiring capacity at high speed and stably.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a data bus circuit according to one embodiment of the invention, and FIG. 2 is a circuit diagram showing a data bus circuit according to another embodiment of the invention. l...First data bus, 2...Second data bus
data bus, Qr, Qs, Qs...n
Channel MOS transistor, Qll...P channel MO3 transistor, 02 to Q4. QB, Qq
, Qs, Q+. ...Bipolar transistor,
Vl...Input signal, V2. V,...selection signal, ■,...output signal, V,,V,...
...Bias voltage.

Claims (1)

[Claims] A pair of data buses consisting of a first data bus with a fixed potential and a second data bus with a variable potential,
A first MOS transistor is connected to the first data bus via a first bipolar transistor,
A second MOS transistor is connected to the second data bus via a second bipolar transistor,
A fixed bias is applied to the base of the first bipolar transistor and the gate of the first MOS transistor, and a selection signal to the data bus is applied to the base of the second bipolar transistor and the gate of the second MOS transistor. Alternatively, a data bus circuit to which a data signal is applied.