JPH03185925A - Clock frequency converter - Google Patents

Abstract

PURPOSE:To lock a PLL(phase locked loop) quickly and to prevent the fluctuation of a generated frequency signal due to oscillation by providing a gate circuit outputting a corrected reference frequency pulse and an up-down counter or the like. CONSTITUTION:A phase comparator 2 compares the output of a 1/2 frequency divider 1 with the output of a 1/32 frequency divider 6 at every logical change point of the output of a 1/2 frequency divider 1 and at a phase 0 of the output pulse of the 1/32 frequency divider 6 and outputs an H level signal while the phase of the 8kHz frequency signal is advanced and outputs an L level signal while the phase of the 8kHz frequency signal is lagged to an up-down counter 3. Then the counter 3 counts the pulse of a frequency 1536kHz twice a reference frequency from a 1/2 frequency divider 4; counts-up while a voltage at a terminal U/D is logical H and counts-down while the voltage at the terminal U/D is logical L. When the count reaches a negative prescribed value, a gate 52 is turned off for a short time, the passing of one pulse in a 768kHz pulse train is blocked and the phase of an output 24kHz is lagged. Thus, the phase of a 24kHz signal is tuned to the phase of an 8kHz to lock a PLL quickly and the fluctuation in the generating frequency due to oscillation is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a clock frequency conversion device.

[Prior Art] In digital wireless communication systems and the like, it may be necessary to convert clock frequencies. For example, in a digital telemeter radio device, the radio section is 8 kbps (kilobits per second), while the communication control section (error code correction and decoding section) is 2.4 kbps, L, 8 kHz.
A conversion of the clock frequency between z and 2.4kHz is required.

These two clock frequencies must be phase synchronized.

Figure 3 is a block diagram showing the configuration of a conventional clock frequency conversion device. In the figure, (21>) is a phase comparator (PD).
, (22) are low-pass filters (LPF), (23> are voltage controlled oscillators (VCO), and (24) and (25> are frequency dividers, respectively).

The VCO (23) oscillates at 24 kHz, and the frequency divider (23) oscillates at 24 kHz.
5>, the phase of the 8K H2 generated by dividing the frequency to 1/3 is compared with the 8kHz of the regenerated clock regenerated from the received signal in the phase comparator (21), and the phase error is converted into an error voltage. LPF (22) VCO (23) - Frequency divider (25) - PD (21) PLL (phase locked loop) L, VCO (23) oscillation frequency 24kHz
z is phase-locked to the reproduced clock of 8 kHz.

[Problems to be Solved by the Invention] Since the conventional clock frequency converter described above is configured as described above, there are problems that it takes time to lock the PLL and that the VCO is susceptible to vibrations, etc. be.

In other words, it usually takes about 100 to 200 m5 for the circuit shown in Figure 3 to start operating and phase lock is achieved, so it is necessary to drastically reduce the current consumption like a digital telemeter wireless device. In some devices, the power to the communication control unit is turned on after entering the reception mode, so data for one or two frames is destroyed during this time.

Furthermore, if the oscillation frequency of the VCO fluctuates due to vibrations, etc., this fluctuation frequency is high, so the PLL shown in Figure 3 cannot suppress this frequency fluctuation, and if an even larger frequency fluctuation occurs, the PLL may become unlocked. be. In order to avoid this problem, if a VCO that is resistant to vibration is used, there are problems such as an increase in price.

The present invention was made to solve this problem, and an object of the present invention is to provide a clock frequency conversion device in which a PLL is quickly locked and the generated frequency does not fluctuate due to vibration.

[Means for Solving the Problems] A clock frequency conversion device according to the present invention uses a phase-locked loop formed by a digital circuit.

[Operation] In this invention, a phase-locked loop using a digital circuit is used, so either a pulse is inserted to lead the output phase of a frequency divider that divides this pulse, or the pulse is deleted and the above By lagging the output phase of the frequency divider, lock-in is quickly performed, and since a vibration generator can be used instead of a VCO, the output frequency is not affected by vibration.

[Examples] Examples of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of this invention. In the figure, (1> is a 172 frequency divider, and (2) is a phase comparator (PD).
, (3) is an up/down counter, (4> is a 1/2 frequency divider, and as described later, this 172 frequency divider (4>) becomes a reference frequency generation circuit. (5) is a gate circuit, and (
51).

It is composed of (52) and (53). (6> is 1/32
A frequency divider, (7> is a 1/10 frequency divider, (8) is a 1/4 frequency divider, and (9>) is a crystal oscillator.

The regenerated clock is 8kHz (generally F), and 2 or 4kHz phase synchronized to this 8kHz (generally M
This circuit outputs F/L) from the frequency divider (7). The crystal oscillator (9) generates 6.144MHz, and the frequency divider (8)
) has a frequency of 1536 kHz, and the output frequency of the frequency divider (4>) is 768 kHz, and this 768 kHz (generally nMF) is temporarily referred to as the base 6-single frequency.

1/32 of 768kHz (generally 1/n) is 24K
Hz and L, this 24kHz is 1/1 by the frequency divider (7).
The second clock frequency is divided by 10 (generally 1/L) to obtain a second clock frequency of 2.4 kHz.

In order to synchronize the phase between the first clock frequency of 8kHz and the second clock frequency of 2.4kHz, a phase comparator (2), an up/down counter (3), and a gate circuit (5) are used.
) is provided, and the output 24kHz of the frequency divider (6) is connected to the frequency divider (
The phase is synchronized to the output 4kHz of 2).

Figure 2 is an operation time chart showing the operation of this phase synchronization, and Figure 2 (a) shows the output waveform of the frequency divider (6〉).
b) represents the output waveform of the frequency divider (1), and (C) of the same figure represents the output waveform of the phase comparator (2>).

The output of the frequency divider (6) i< Compared to the phase 0 point of
'', while there is a lag in the phase of 8kHz2, logic rl and J signals are output and input to the U/D terminal of the up/down counter (3).

The up/down counter (3) counts pulses with a frequency of 1536 kHz, which is twice the reference frequency, and counts up while the voltage at the terminal U/D is rH, and counts down while it is "L".

At time t1 in Fig. 2, the count value of the up/down counter (3) reaches a positive predetermined value, and the gate (51) is turned on for a short time.
Insert into Hz pulse train.

The frequency division in the frequency divider (6) is advanced by one pulse, and t
At time point 2, the output of the phase comparator (2) becomes logic "L".
, the up/down counter (3) starts counting down.

In this way, when the count value of the up-down counter (3) reaches a predetermined negative value, the up-down counter (3)
) turns off the gate <52> for a short time and generates 768k.
One pulse in the Hz pulse train is blocked from passing.

Frequency division of frequency divider (6) is delayed by one pulse, output 24kHz
There is a lag in the phase of z.

Through the feedback control described above, the 24 kHz phase is synchronized with the 8 kHz phase, and therefore the 2.4 kHz phase is synchronized with the 8 kHz phase.

However, phase discontinuity occurs when one pulse is inserted or deleted in the gate circuit (5), but the frequency divider (6)
The influence of discontinuity can be avoided by appropriately increasing the frequency division ratio of >.

The stability of this digital PLL system can be maintained by appropriately selecting a predetermined number of positive or negative counts that the up/down counter (3) should reach in order to output control pulses to the gate circuit (5). In one design example, phase lock can be achieved in about 2 ms from the start of operation.

Note that the circuit shown in FIG. 1 can be easily integrated into an IC.

[Effects of the Invention] As explained above, this invention significantly reduces the time required for phase locking compared to the conventional one, and therefore improves the reliability of the communication system. It has the advantage that it is strong against vibrations and can be constructed with a simple circuit.

[Brief explanation of drawings]

Fig. 1 is a process diagram showing one embodiment of the present invention;
The figure is an operation time chart for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a block diagram showing a conventional device. 2... Phase comparator, 3... Up/down counter,
4...1/2 frequency divider (reference frequency generation 10-

Claims (1)

[Claims] A clock frequency conversion device that generates a second clock frequency MF/L (where L and M are each arbitrary integers) phase-synchronized with the first clock frequency from a first clock frequency F. , a reference frequency generation circuit that generates an accurate frequency of frequency nMF (where n is a relatively large integer, for example, 32); one pulse is inserted for every predetermined number of output pulses of this reference frequency generation circuit; Or a gate circuit that outputs a reference frequency pulse corrected by removing one pulse or passing the output pulse of the reference frequency generation circuit as it is, and the output pulse of this gate circuit is
/n to output the corrected frequency MF
A frequency divider, which compares the output pulse of this 1/n frequency divider with the phase of the first clock frequency pulse, and increments the up/down counter when the phase of the first clock frequency pulse is leading. a phase comparator that operates as a counter and causes the up/down counter to operate as a down counter when the phase of the first clock frequency pulse lags; When the counted value is between a positive predetermined value and a negative predetermined value, the gate circuit allows the output pulse of the reference frequency generation circuit to pass through as it is, and the counted value reaches the positive predetermined value. When this happens, one pulse is inserted into the output pulses of the reference frequency generation circuit, and when the counted value reaches the negative predetermined value, one pulse is removed from the output pulses of the reference frequency generation circuit. A clock frequency conversion device characterized by comprising: means for controlling the clock frequency so that