JPH0318683U - - Google Patents
Info
- Publication number
- JPH0318683U JPH0318683U JP7813289U JP7813289U JPH0318683U JP H0318683 U JPH0318683 U JP H0318683U JP 7813289 U JP7813289 U JP 7813289U JP 7813289 U JP7813289 U JP 7813289U JP H0318683 U JPH0318683 U JP H0318683U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- integrated circuit
- phase input
- output
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
Landscapes
- Bipolar Integrated Circuits (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の第１実施例の集積回路の回路
図、第２図は第１実施例の集積回路の動作波形図
、第３図は本考案の第２実施例の集積回路の回路
図、第４図、第５図は本考案の第１実施例の集積
回路の第３、第４の応用例の回路図である。第６
図は従来の集積回路の回路図である。
ＩＣ１，ＩＣ２……集積回路、１〜４……外部
導出端子、Ｑ……直列制御用素子（ＰＮＰトラン
ジスタ）、Ｑ１……ヒステリシス付加用トランジ
スタ、ＯＰ……差動増幅器、ＶＲ……内部基準電
圧源、ＲＸ，ＲＹ，Ｒ１，Ｒ２……抵抗、Ｄ……
転流用ダイオード、Ｌ……積分用インダクタンス
、Ｃ１……出力平滑用コンデンサ、Ｖｉ……入力
電源、ＶＣ……制御信号、Ｚ……負荷、Ｘ……定
電圧出力端子（チヨツパ型電源）。
Fig. 1 is a circuit diagram of an integrated circuit according to a first embodiment of the present invention, Fig. 2 is an operation waveform diagram of an integrated circuit according to a first embodiment, and Fig. 3 is a circuit diagram of an integrated circuit according to a second embodiment of the present invention. 4 and 5 are circuit diagrams of third and fourth application examples of the integrated circuit according to the first embodiment of the present invention. 6th
The figure is a circuit diagram of a conventional integrated circuit. IC1, IC2...Integrated circuit, 1 to 4...External lead-out terminal, Q...Series control element (PNP transistor), Q1...Hysteresis addition transistor, OP...Differential amplifier, VR...Internal reference voltage Source, RX, RY, R1, R2...Resistance, D...
Commutation diode, L...integrating inductance, C1...output smoothing capacitor, Vi...input power supply, VC...control signal, Z...load, X...constant voltage output terminal (chopper type power supply).
Claims (1)
、且つ基準電圧源と、基準電圧と出力電圧を比較
、増幅する差動増幅器を有し、差動増幅器の出力
で前記直列制御用素子をオン、オフ制御して出力
電圧を制御する集積回路において、 前記差動増幅器の逆相入力端とＧＮＤ間に基準
電圧源を接続し、正相入力端を直接導出する端子
を設け、且つ正相入力端に抵抗を接続し、この抵
抗の他端をヒステリシス付加用トランジスタを介
してＧＮＤに接ぎ、このヒステリシス付加用トラ
ンジスタの制御電極を抵抗を介して前記出力端子
に接続したことを特徴とする集積回路。 (2) 前記差動増幅器の正相入力端を、抵抗を介
して外部端子に接続するとともに他の抵抗を介し
てＧＮＤ端子に接続したことを特徴とする請求項
１記載の集積回路。[Claims for Utility Model Registration] (1) It has a series control element between the input and output terminals, and has a reference voltage source and a differential amplifier that compares and amplifies the reference voltage and the output voltage. In the integrated circuit that controls the output voltage by controlling the series control element on and off using the output of the amplifier, a reference voltage source is connected between the negative phase input terminal of the differential amplifier and GND, and the positive phase input terminal is connected to the ground. A resistor is connected to the positive phase input terminal, the other end of this resistor is connected to GND via a hysteresis adding transistor, and the control electrode of this hysteresis adding transistor is connected to the output via the resistor. An integrated circuit characterized by being connected to a terminal. (2) The integrated circuit according to claim 1, wherein the positive phase input terminal of the differential amplifier is connected to an external terminal via a resistor and to a GND terminal via another resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7813289U JPH073831Y2 (en) | 1989-06-30 | 1989-06-30 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7813289U JPH073831Y2 (en) | 1989-06-30 | 1989-06-30 | Integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0318683U true JPH0318683U (en) | 1991-02-25 |
| JPH073831Y2 JPH073831Y2 (en) | 1995-01-30 |
Family
ID=31621132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7813289U Expired - Lifetime JPH073831Y2 (en) | 1989-06-30 | 1989-06-30 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073831Y2 (en) |
-
1989
- 1989-06-30 JP JP7813289U patent/JPH073831Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH073831Y2 (en) | 1995-01-30 |
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