JPH03186954A - Address error detection system - Google Patents

Abstract

PURPOSE:To detect an address error owing to a fault after an address switching circuit at the time of reading by generating a check bit from an address parity bit and data which are generated for respective addresses that are time-divided at the time of writing and writing them with data into a memory. CONSTITUTION:At the time of writing, address parity generation circuits 1-1 and 1-2 generate the address parity bits for respective addresses which are time-divided and a check bit generator 2 generates the check bit from data and the address parity bits and writes data and the check bits into the memory 3. At the time of reading, a syndrome generator 6 generates a syndrome code from data and the check bits, both of which are read from the memory 3, and the address parity bits for respective addresses for time division, which are to be read, and detects the address error. Thus, the address error owing to the fault after the address switching circuit 4 is detected.

Description

[Detailed Description of the Invention] [Summary] Regarding the 7-trace error detection method for detecting address errors in data read from memory, check bits are generated from address parity bits and data generated for each time-divided address during writing. The purpose of this is to enable the detection of address errors due to failures in the address switching circuit and subsequent circuits.Address validation 7 is applied to each time-sharing address for writing data to memory. ), generates a check pin from these generated address parity bits and data, and writes it to the memory together with the data, the address parity bit for each address that is time-divided during reading, the data read from memory, and the check hit. Configure to detect address errors based on .

[Industrial application field]

The present invention relates to an address error detection method for detecting a 71' error in data being retrieved from a memory.

[Prior art and problems to be solved by the invention] Conventionally, when writing data to a memory, data is written from (n+1) bits (n data bits plus one address parity bit) to (m bits). Write the data (n bits) and check bits (m bits) to -1 (n m) bits.
Add 1 bit of data read from memory, check bit (m bit), and address parity bit of the address to be read (n+m+
1) Generate a syndrome code from the bits by referring to the syndrome code table. At this time, if data is written to a different address than the address you tried to write to, or if data is written to a different address than the address you tried to read from, the address at the time of memory write determined from the syndrome code generated above. Since the parity is different from the address parity at the time of memory read, address errors can be easily detected.

However, a DRAM that writes data by dividing the address into an upper address and a lower address and supplying it
In this case, there is a problem that an address parity error cannot be detected when a failure occurs after the switching circuit that switches between the upper address and the lower address. For example, row address X “00” becomes X “01”, column address X “0”
0” becomes X“01” and the correct address is X“0000”
Even if the wrong address X "0101" is read instead of address "0101", there is a problem in that the address error cannot be detected because both address parities are the same.

The present invention generates a check bit from the address parity bit and data generated for each time-divided address during writing and writes it into memory together with the data, making it possible to detect address errors due to failures in the address switching circuit or later. The purpose is to

[Means to solve problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, address parity generation circuit 11, ]-
2 generates an address parity bit for each address to be time-divided.

The check bit generator 2 generates check bits from data and address parity bits.

The memory 3 is a memory (for example, DRAM) in which addresses are supplied in a time-division manner to write data.

The syndrome generator 6 generates a syndrome code (a code for detecting address errors, etc.) from the data read from the memory 3, check bits, and address parity bits for each time-divided address to be read.

[Effect]

In the present invention, as shown in FIG. 1, address parity generation circuits 1-1 and 1-2 generate address parity bits for each time-divided address during writing, and a check bit generator 2 generates data and these address parity bits. Generates a check bit from memory 3 and writes the data and this check bit together to memory 3. At the time of read, syndrome generator 6 checks the data read from memory 3, checks the focus, and writes the check bit to memory 3. A syndrome code is generated from the address parity bit of the address to detect address errors.

Therefore, a check bit is generated from the address parity bit and data generated for each time-divided address at the time of writing, and the check bit is stored in the memory (for example, DRAM) 3 along with the data.
By writing to , it is possible to detect address errors due to failures in the address switching circuit and subsequent circuits.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 and 2.

In FIG. 1, address parity generation circuit 11.1-
2 generates an address parity bit for each upper address and lower address to be time-divided.

The check bit generator 2 converts the data and address parity bits into the check pinpoint code shown in FIG. 2(a).
1" Refer to the table and check the check bits (for example, Fig. 2 (a)
7-bit check bits consisting of CI to C7 shown in FIG.

Memory 3 is a memory (for example, D
RAM).

The address switching circuit 4 uses CP during writing/reading.
The address notified from U etc. is the upper address (RAS).
) and lower addresses (CAS), and sequentially supply them to the memory 3 via the 71 bus sofa 5.

The syndrome generator (SG) 6, when reading,
Based on the data read from memory 3, the check bit, the address parity bit of the upper address of the address to be read, and the address parity bit of the lower 71 address, refer to the syndrome code table in Figure 2 (b). Syndrome codes (for example, syndrome codes S1 to S7 in FIG. 2(b)) are generated using the synchronization process.

Detection of address errors, etc. is performed from this system 1' roam code 1'.

The data collector 7 detects whether there are any errors in data or address parity bits, detects and repairs 1-bit errors, or detects multi-bit errors based on the syndrome code 1. be.

Next, a specific example will be explained with reference to FIG.

(1) When writing to the nearest address X “0101” (address width is 32 bits) during memory write, the address parity bit “0” of the upper address X “01” (assumes odd parity, the same applies hereafter), and Generate address parity bit "0" for lower address X "01". These raw address parity bits “OO” and data X “ooooo.”

00", generate check bit
ooooooooo” and this check hit X “00
'' are written to address X"0101" in memory 3. In FIG. All the values (■ or 0) of the parity bit part are extracted, and an exclusive OR operation is sequentially performed on all the extracted values.

(2) When reading near address X “0000” (address width is 32 bits), upper address X “00”
The address parity bit "1" (odd parity) of the lower address X "00" and the address parity bit "1" of the lower address X "00" are generated.

At this time, for example, due to a failure of the address 8 sofa 5 in FIG. ooooooooo” and check hit X “00”. This read check bit X "00" is the check focus when both upper/lower address parity bits are "O", so these data X "oooo".

000", check bit x"oo++, and 7 address validity bit "11" when reading are input to the syndrome generator 6 in Figure 1, the syndrome code is X"7E' with reference to Figure 2 (B). Since the syndrome code is not 0'' and does not correspond to any one-bit error (in this case, when three bits are 1), it is detected as a multi-bit error (in this case, the parity of the upper address of the address is This results in an error in both the bit and the parity bit of the lower address).

As described above, address parity bits are generated for each upper address and lower address that time-divide addresses during writing, check bits are generated from these address parity bits and data, and the check bits are sent to the memory 3 along with the data.
Generates a syndrome code based on the data read at the time of reading, the check bit, and the address parity bit for each time-divided address of the address to be read, and generates an address for each time-divided address. By detecting errors and data errors and automatically repairing 1-bit errors, it is also possible to detect address errors due to failures in the address switching circuit 4 and subsequent parts when writing addresses to the memory 3 in a time-divided manner.

FIG. 2(A) shows an example of a check bit code table. Here, O to 31 in the data column represent O bits to 31 bits of the data to be written, and P in the data column
1 and P2 represent the address parity bit of the upper atlas and the address parity bit of the lower address of the address to be written. C1
to C7 represent a 7-bint check code. The value of each of these check codes CI to C7 is “1” in each row.
This is the result of extracting all the data in which `` is set, or in other words, the values (O or ]) of the cell parity bit part, and sequentially performing an exclusive OR operation on these extracted values.

For example, when finding the check code C1, “
All 13-bit values from 4.6.7...Pl of the data where '1' is set are extracted. (2) Sequentially perform exclusive OR operations on all these retrieved values, and obtain the result as check code C1.

FIG. 2 (r3) shows an example of a syndrome code table. Here, 0 to 31 in the data column represent bits 0 to 31 of the data read from memory 3, and Pl and P2 in the data column are the address parity bit of the upper address of the address to be read, and the lower It represents the address parity pit 2 of the address, and C1 to C7 are the 7 bits read from memory 3.
Represents the bit check code. Vertical 31 to S
7 represents a syndrome code.

The value of each of these syndrome codes S1 to S7 is obtained by extracting all the values (0 or 1) of the data, address parity bit, and check code part of each row in which "1" is set, and then using the exclusive OR of these extracted values. This is the result of sequential calculations.

In addition, when syndrome codes S1 to S7 are all 0, there is no error. Furthermore, if any three bits of syndrome codes S1 to S7 are “l”, these three bits are “l”.
Bit “■” stands for data 0 to 31, Pl
, P2 is found to be a 1-bit error, and is automatically repaired. In cases other than these, it is detected as an error of 2 or more bits (multi-bit error).

〔Effect of the invention〕

As described above, according to the present invention, a configuration is adopted in which a check bit is generated from the address parity bit and data generated for each time-divided address during writing, and is written to the memory (for example, DRAM) 3 together with the data. Therefore, address errors due to failures in the address switching circuit and subsequent circuits can also be detected during reading.

[Brief explanation of drawings]

FIG. 1 shows a configuration diagram of one embodiment of the present invention, and FIG. 2 shows an example of a code table according to the present invention. In the figure, 1-1.1-2 is an address parity generation circuit;
is a check bit generator, 3 is a memory, 4 is an address switching circuit, 5 is an address buffer, and G is a sink I.
'Roam generator, 7 represents data collector.

Claims (1)

[Claims] In an address error detection method for detecting address errors in data read from memory, address parity bits are generated for each time-sharing address for writing data to memory, and the generated address parity bits are Generates a check bit from the data and data and writes it to memory together with the data, and detects address errors based on the address parity bit for each address that is time-divided during reading, the data read from memory, and the check bit. An address error detection method characterized by being configured to detect an address error.