JPH03186961A - I/o interruption control system in multi-processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding the I/O interrupt control method for controlling the generation of I/O interrupts in multiprocessors, the CH of each processor is By performing an operation with the allocation mask and causing any I processor to perform processing by exclusively generating an interrupt, the I/O
The purpose is to eliminate the burden of canceling I/O interrupt processing on processors that do not accept interrupts, and to improve processing efficiency in multiprocessors.
Each processor is provided with a CH allocation mask having a mask bit indicating whether to exclusively accept interrupts from an I/O device (or a CI (device)), and the CH allocation mask is configured in response to an interrupt request from an I/O device. The configuration is such that only a processor that accepts an interrupt by performing an operation with a stored mask bit generates an interrupt and performs processing, and prevents other processors from generating an interrupt.

[Industrial application field]

The present invention relates to an I/O interrupt control method for controlling the occurrence of I/O interrupts in a multiprocessor.

In recent years, with the demand for processing large amounts of data in computer systems, there has been a demand for connecting a large number of I10 devices to a multiprocessor to process large amounts of data at high speed. At this time, I/O interrupt control with high processing efficiency is desired.

[Conventional technology]

I/O interrupt control in conventional multiprocessors is
When an interrupt request is received from an I10 device, as shown in Figure 4, an interrupt is generated in all interrupt-enabled processors (■, O), and the I/O interrupt processing authority is granted during the processing of these interrupts. Only the one processor that obtained the interrupt notification to the software (0, ■YES, ■), and the other processors canceled the interrupt processing (0, ■N010>).

In FIG. 4, H3A (bar 1' hardware system area) is a memory area for hardware control that cannot be accessed from software on the MSU (main memory).

[Problem to be solved by the invention]

For this reason, processors other than the processor that notifies the software of I/O interrupts have to perform the extra work of canceling I/O interrupt processing, resulting in a problem of lowering the processing efficiency of the multiprocessor. .

The present invention responds to interrupt requests from ■/○ devices by
Cancellation of I/O interrupt processing of a processor that does not accept I/O interrupts by performing calculations with the CH allocation mask of each processor and causing any one processor to exclusively generate and process interrupts. The aim is to eliminate the burden caused by this and improve processing efficiency in multi-processor sensors.

[Means to solve problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, the allocation mask 6 is a mask having mask bits indicating from which I10 device (or CH device) interrupts are exclusively accepted, and is provided in each processor 1, respectively.

The I10 device is for making I/O interrupt requests.

[Effect]

As shown in FIG. 1, the present invention, in response to an interrupt request from an l/○ device, performs an operation with the mask bits stored in the allocation mask 6 to issue an interrupt only to the processor 1 that accepts the interrupt. is generated to perform processing, and prevents interrupts from being generated to other processors.

Therefore, in response to an interrupt request from an I10 device, the 170 interrupt This eliminates the burden of canceling I/O interrupt processing of processors that do not accept requests, and improves processing efficiency in multiprocessors.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 3.

In FIG. 1, a processor 1 performs various processes, such as notifying software (processing program) of I/O interrupts based on the μ program, and performing various processes under the software. It is something to do. This processor 1
(for example, 4 units), one I10 control device (IO
P, Input Output Processor〉 2 to configure a multiprocessor system, and respond to interrupt requests from I/O devices via channel (CH) 7 to only one processor. Processing is performed by exclusively generating interrupts.

The CH mask 3 is used to set mask bits set by software to determine which channel 7 is to be accepted as an interrupt. Normally, all channels are set to 1 to enable reception.

The CH allocation mask 6 sets mask bits indicating which channel 7 (or I10 device) the processor 1 will exclusively accept I/O interrupts from.

The CI allocation control unit 5 controls the CH allocation mask 6 by transmitting 170 signals from any channel 7 (or I10 device).
A mask bit indicating whether to accept an interrupt request is set in the C8 sharing mask 6, and furthermore, mask pins 1 to 1 are shifted in a circular manner at predetermined time intervals to make the load sharing among each processor as uniform as possible. It is.

When there is an I/O interrupt request, the I/O interrupt control unit 4 sends 1.
This generates 10 interrupts.

The I10 control device (IOP) 2 is placed between the plurality of channels 7 and the plurality of processors 1 to control data input/output. It is composed of an interrupt control section 2-1 and the like.

The channel (CH) 7 is placed between the multiple I10 devices and the I/O control device 2 to perform data output control, and here, the I/O interrupt request is sent to the T/○ control device. W
2, etc.

The I10 device is a device that inputs and outputs data.

Next, the operation of the configuration shown in FIG. 1 will be explained in detail using the flowchart shown in FIG.

In Figure 2, [phase] is the I10 control device (IOP)
2 notifies processors #0 to #3 of an I/O interrupt request. This is done via channel 7 from the I/O device in FIG.

P) In response to an interrupt request in 2, the corresponding I1
0 control device 2 notifies all four processors #0 to #3 of an I/O interrupt request. In response to this I/O interrupt request, only processor #O exclusively generates an interrupt and notifies the software, and the remaining processors #1 to #3 do not generate interrupts. The operation when setting the CH allocation mask 6 in FIG. 1 will be described below.

■ sends notification of I/O interrupt request of [phase] to processor #
0 receives.

@ performs a logical product operation of CH allocation mask & CH mask. Here, the result of the AND operation is “1” and YES
Then, perform ■.

(2) causes an I/O interrupt to be generated in the μ program.

In (2), the μ program notified by the I/O interrupt at 0 notifies the software that there has been an interrupt from a predetermined I10 device (channel 7), and causes it to perform input/output processing.

Then, the next instruction is processed.

By the above processing of 0 to [phase], l10IIHI
In response to an I/O interrupt request from the I device 2, an I/O interrupt is generated exclusively to processor #0 for which the corresponding mask bit of the C8 sharing mask 6 is "1" and processing is performed. By setting I
/O interrupt processing can be performed efficiently.

■Sends notification of I/O interrupt request of [phase] to processor #
1 to #3 will receive it.

In [phase], the AND operation of the CH allocation mask & CH mask is performed in each of the processors #1 to #3. Here, the result of the AND operation is "0", which is No, and the next instruction is processed without generating an I/O interrupt.

As a result of the above process ① and 0, in response to the I/O interrupt request from the I10 control device 2, the processors #1 to #3 whose corresponding mask bits in the CH allocation mask 6 are “O” are By terminating the process without generating an /O interrupt, it becomes possible to eliminate unnecessary I/O interrupt processing.

FIG. 3 shows a schematic diagram of one embodiment of the present invention. Here, processor 1 indicates the configuration of one of three processors.

In FIG. 3, the CH allocation control circuit 5-1 controls the CR transmitted from the TOD (timer) 5-2 every predetermined period of time.
Corresponding to YN (carry from timer bit N), set 1 to SFT (1-bit circular shifter) 6-2.
It notifies a bit shift signal and shifts the mask focus set in CHDM (Cf (shared mask) 6-1 in a circular manner by one bit. As a result, CHDM (C8 share mask) 6 to Since the contents of the mask focus set on the
The processors 1 that accept interrupt requests are sequentially changed, and load distribution can be made uniform.

CH mask 3-1 includes I from Cl-1 (channel 7).
/O This is a mask that sets mask bits to determine whether or not to accept interrupt requests. I/O interrupts are accepted for CHs set to (2), and I/O interrupts are not accepted for CHs set to 0. Normally, all mask bits of the CH mask 3-1 are set to "l".

The I/O interrupt control circuit 4-1 receives mask bits from the CH mask 31 and CHDM (shared mask bits) 6-■
and the I/O interrupt request from the IOP (I10 control unit 2), and an I/O interrupt is generated for the corresponding channel for which the result of the logical product is “1” (Figure 2 @
YES, 0).

In the above configuration, when an I/O interrupt request is notified from the I10 control device 2 to the processor 1, the I/O interrupt request, the mask bit of CHDM (C8 sharing mask) 6-1, and the mask bit of CH mask 3I are (mask via), and only when the result 2 is "1", the ■/○ interrupt control circuit 41
Generates an I/O interrupt to the program and performs I/O to the software
An interrupt is notified and the corresponding channel (I10 device) is made to perform input/output processing.

〔Effect of the invention〕

As explained above, according to the present invention, in response to an interrupt request from an I/○ device, an operation is performed with the CH allocation mask 6 possessed by each processor, and an interrupt is exclusively sent to any one processor. Since a configuration is adopted in which processing is performed by generating an I/O interrupt, it is possible to eliminate the burden of canceling I/O interrupt processing of a processor that does not accept I/O interrupts, and to improve processing efficiency in a multiprocessor.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle configuration of the present invention, Figure 2 is an I/O diagram of the present invention.
FIG. 3 shows a flowchart of an interrupt processing according to an embodiment of the present invention, and FIG. 4 shows a conventional I/O interrupt processing flowchart. In the figure, 1 is a processor, 2 is an I10 control device (IOP)
, 3 is CH lower mask 4 is I/O interrupt control section, 5 is C
H sharing control unit, 6 is C8 sharing mask, 7 is channel (C
H).

Claims (1)

[Claims] In an I/O interrupt control method for controlling the occurrence of I/O interrupts in a multiprocessor, any I/O interrupt is controlled in response to an interrupt request from an I/O device.
CH allocation mask (6) with a mask bit indicating whether to exclusively accept interrupts from the O device (or CH device)
is provided in each processor, and in response to an interrupt request from an I/O device, performs an operation with the mask bits stored in the CH allocation mask (6) and generates an interrupt only to the processor that accepts the interrupt. 1. An I/O interrupt control method for a multiprocessor, characterized in that the I/O interrupt control method for a multiprocessor is configured such that a processor is caused to perform processing without causing an interrupt to other processors.