JPH03187070A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To output a correct address signal even at the time of abnormality of error detection by comparing a forecasted address signal and an actual reproduced signal with each other in every frame and outputting the latter instead of the former at the time when disaccord continues over a prescribed threshold. CONSTITUTION:The reproduced address signal from an address signal extracting circuit 3 and the forecasted address signal outputted from a forecasting circuit 5 are compared with each other by a comparing circuit 8; and if they so not coincide with each other, a disaccord signal is counted by a counting circuit 9. The forecasted address signal is always outputted in the normal state, and the normal address signal is outputted though error occurs in the reproduced address signal and erroneous detection occurs in an error detecting circuit 4. If the address signal is broken because of joint recording at the time of recording, the reproduced address signal is selected by a selecting circuit 7 because the output of the circuit 9 exceeds the threshold, and the address signal is forecasted based on this reproduced address signal hereafter.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a reproduction signal processing circuit in a digital signal recording and reproduction apparatus.

(b) Conventional technology In devices that record and reproduce digital signals, the second
It is recorded in a frame as shown in Figure (a).

One frame consists of a synchronization signal, an address signal, a digital signal to be recorded, an error correction code for this signal, and the like. During playback, a synchronization signal is detected, frame synchronization is established, and the digital signal is processed in accordance with the address signal. For example, in a digital VTR that digitally encodes and records video signals, this address signal is used to determine which position within one screen the video signal data is located at. Therefore, if an error occurs in this address signal, the video cannot be reproduced normally.

As a countermeasure to this problem, Japanese Patent Application Laid-Open No. 58-99080 (G11B
5109) r Digital video signal processing apparatus" may be considered. This method will be explained with reference to FIGS. 4 and 5. This is an address signal processing circuit in a digital VTR that records and reproduces video signals using a rotating head.
This protects address signals during tracking. As shown in FIG. 5(a), N frames of data are recorded in one track, and frame numbers from ■ to N and error check codes for these frame numbers are recorded as address signals. During playback, address signal extraction and error detection are performed by the address identification/judgment circuit (16) shown in FIG. Further, the prediction circuit (17) predicts the address signal of the next frame from the address signal of the previous frame, as shown in FIGS. 5(b) and 5(C).

Then, according to the error detection result of the address identification judgment circuit (16), the switch (18)
) and the output of the prediction circuit (17) are switched.

When an error in the address signal is detected, the prediction circuit (17)
output is selected.

In this way, when an error occurs in the address signal,
Address signals are protected by replacing them with predicted values from the previous frame.

(c) Problems to be Solved by the Invention The method described in the previous section detects errors in the address signal using an error check code added to the address signal. However, when the code error rate during reproduction increases, there is a possibility that the error check code will make a wrong check decision. In other words, a case may occur in which incorrect data is determined to be correct (hereinafter referred to as erroneous detection). If this erroneous detection occurs, the method described in the previous section will output an erroneous address signal, causing a problem. Further, in order to reduce the probability of false detection, it is possible to add a check code with a large inter-code distance, but this is not preferable because the code length of the check code becomes long and the amount of recorded data increases.

(d) Means for solving the problem The present invention is comprised of the following technical means. First, a synchronization detection circuit detects a synchronization signal from a reproduced signal. Based on this, the address signal portion is extracted and inputted to the first input terminal of the selection circuit. An error detection circuit detects code error 12 in the extracted address signal. Also,
A circuit for predicting the next frame's address signal from the previous frame's address signal is provided, and this predicted address signal is input to the second input terminal of the selection circuit. The comparator circuit compares the signals of the first human power and the second human power of the selection circuit, and outputs a mismatch signal when the results are not equal. A counting circuit counts how many frames this mismatch continues. Note that this counting is not performed if the error detection circuit determines that there is an error. The control signal generation circuit usually outputs a control signal so that the second input of the selection circuit is selected, and controls the first input of the selection signal to be selected when the counting result exceeds a certain predetermined threshold. Output a signal.

Furthermore, when reproducing at a speed higher than the reproducing speed during recording, such as high-speed reproducing or low-speed reproducing, the threshold value is controlled according to the state.

(E) Function Normally, when the address signal is correctly output from the address signal extraction circuit, the reproduced address signal and the predicted address signal match, and the output of the counting circuit is O. Therefore, the selection circuit selects the predicted address signal. When an error occurs in the address signal and erroneous detection occurs in the error detection circuit, the erroneous address signal is input to the selection circuit and the comparison circuit. At this time, the number of mismatches is counted, and the predicted address signal is selected until the counting result reaches a predetermined value. Therefore, even if an erroneous detection occurs, this address signal is not selected and a normal address signal is output.

However, due to continuous shooting during recording, the address signal may become discontinuous in the middle. At this time, since the mismatch signals continue, the count result exceeds the threshold value, the output from the address signal extraction circuit is selected, and prediction is thereafter performed based on this address signal.

(F) Embodiment As an embodiment of the present invention, an example in which the present invention is applied to a digital VTR that records digitally encoded video signals using a rotary head will be described with reference to FIGS. 1 to 3. FIG. 2(a) shows one frame recorded on a magnetic tape. Synchronization signal (12), address signal (]3), video signal (14), and error correction code (1) for the video signal
5) constitutes one frame. Also, Figure 2(b)
As shown in the figure, X frames are recorded on one track. This frame number is assumed to be from O to N-1, and the address signal (13) is composed of this frame number and an error check code.

FIG. 1 is a block diagram showing an embodiment of the present invention. A signal reproduced from a magnetic tape and subjected to processing such as waveform equalization is input to an input terminal (1). The synchronization detection circuit (2) detects a synchronization signal added to each frame. At this time, synchronization protection is performed so that even if a code error occurs in the reproduced signal, the synchronization signal will not be dropped. Based on this synchronization signal, an address signal extraction circuit (3) extracts the address signal portion. Thereafter, an error detection circuit (4) detects a code error in the address signal. The prediction circuit (5) has an input terminal (6
) is reset by the scan start signal inputted from ), and then outputs a value obtained by adding 1 to the address signal of the previous frame. The scan start signal is a signal indicating the initial position of the track, and is generated by detecting the rotational phase of the rotary head. The reproduced address signal output from the address signal extraction circuit (3) and the predicted address signal output from the prediction circuit (5) are input to a selection circuit (7) and a comparison circuit (8), respectively. A comparison circuit (8) compares these two address signals and outputs a mismatch signal when they are not equal. A counting circuit (9) counts whether or not this mismatch signal continues in each frame.

Note that this counting is not performed when a code error is detected by the error detection circuit (4). The control signal generation circuit (10) outputs a signal for controlling the selection circuit (7). When the count value is below a predetermined threshold value, control is performed to select the predicted address signal, and when the count value exceeds the threshold value, a control signal is outputted so as to select the reproduced address signal. This selection result is output from the output terminal (11).

By using the above processing circuit, a predicted address signal is always output under normal conditions, and a normal address signal can be output even if an error occurs in the reproduced address signal and an erroneous detection occurs in the error detection circuit. . In addition, when the address signal becomes discontinuous during recording, etc., the output of the counting circuit (9) exceeds the threshold, so the playback address signal is selected, and from now on, based on this address signal, Predictions will be made. In addition, when adding a code capable of error correction instead of an error check code to the address signal, error correction is performed using this code, and when it is determined that the code is uncorrectable, the uncorrectable signal is sent to the error detection circuit ( It is sufficient to replace it with the output of 4).

Furthermore, when performing high-speed reproduction or low-speed reproduction, the signal is reproduced across the tracks recorded on the tape, as shown in FIG. Therefore, when moving to an adjacent track, the address signal may become discontinuous. When performing such reproduction, the threshold value in the control signal generation circuit (10) is kept small. This makes it possible to immediately shift to a correct address signal when the address signal becomes discontinuous. However, in this case, the degree of protection of the address signal is reduced. Therefore, during normal speed reproduction, the threshold value is increased to increase the protection of the address signal, and during high speed/low speed reproduction, the threshold value is decreased.

In this way, address signals can be processed according to the reproduction state.

(g) Effects of the Invention By using the processing circuit of the present invention, a correct address signal can be output even if error detection in the address signal is not performed normally. Furthermore, since it is possible to change the degree of protection of the address signal, it is possible to perform processing according to the reproduction state.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram explaining the frame number and track tIl command in the embodiment, FIG. 3 is a diagram showing the track pattern recorded on the tape, and FIG. The figure is a block diagram showing an example of a conventional technique, and FIG. 5 is an explanatory diagram illustrating the conventional technique. 4...Error detection circuit, 5...Prediction circuit, 7...Selection circuit, 8...Comparison circuit, 9...Counting circuit.

Claims (2)

[Claims] (1) A playback processing circuit in a device that records and plays back a digital signal by adding a synchronization signal, an address signal, etc. to form a frame, and usually outputs an address signal predicted from the address signal of the previous frame. The predicted address signal and the actually reproduced address signal are compared frame by frame, and when the comparison result shows a continuous mismatch of more than a predetermined threshold, the predicted address signal is compared with the actually reproduced address signal. A digital signal reproduction processing circuit characterized in that it outputs an address signal and thereafter performs prediction based on the address signal. (2) The digital signal reproduction processing circuit according to item 1, wherein the threshold value for the number of continuous discrepancies is changed between normal speed reproduction and high speed or low speed reproduction.