JPH03187097A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the number of the terminal for chip selecting signal and to reduce a packaging area by incorporating a circuit generating the chip selecting signal from a synchronous signal in a semiconductor memory. CONSTITUTION:The synchronous signal of square wave enters from a CLK terminal to the memory. By a capacity 7 and a resistor 8 the memory is charged and discharged with a higher potential than the inverse potential of an invertor 9, the invertor 9 outputs the potential of L level. When no input of the synchronous signal is prevent on the CLK terminal, and the constant voltage is inputted there, the potential lower than its inverse potential is inputted to the inverter 9, so that the inverter 9 outputs the potential of H level. In other words, a CS signal generating circuit 5 outputs L or H level in accordance with the existence of the input signal and with read/write signal the data terminal can be controlled to the input, output and the high impedance state. Consequently, the semiconductor memory 1 can be switched to each state of the acting/waiting. In this constitution the selective signal is eliminated, the terminal can be omitted, and the packaging area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory capable of serial input/output of data.

[Summary of the invention]

The present invention provides a semiconductor memory that serially inputs and outputs data, by incorporating a circuit that can generate a chip select signal from a synchronization signal necessary when inputting and outputting data to the semiconductor memory. This eliminates the need for a special chip select signal.

[Conventional technology]

Conventionally, when attempting to realize a semiconductor memory that serially reads and writes data, at least the following terminals were required.

1, Vcc (power supply terminal) 2, GND 3, DATA (data input/output terminal) 4, CLK (synchronous signal input terminal with data) 5゜C3
(Active, standby control signal) 6. R/W (Data read/write control) [Problem to be solved by the invention] However, when operating the semiconductor memory of the prior art, the signal source input to CLK and C3 is had to be prepared for each person.

[Means to solve the problem]

In order to solve the above problem, the present invention incorporates a circuit for generating the C8 signal from the CLK signal inside the semiconductor memory, thereby eliminating the need to provide a signal source for the CS signal externally.

[Effect]

The semiconductor memory according to the present invention internally generates an active C3 signal when a synchronization signal is input to the CLK terminal,
Enables serial data input/output. Furthermore, if a synchronizing signal is not input to the CLK terminal and a constant level potential is supplied, a standby C8 signal is generated and serial data cannot be input or output.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

The semiconductor memory l shown surrounded by a dotted line in FIG. 1 includes an address decoder 2, a memory cell 3, a data input/output buffer 4,
A chip select signal generation circuit 5 is provided.

The chip select signal generation circuit 5 includes a reverse current blocking diode 6, a capacitor 7 that determines the charging/discharging time constant, a resistor 8,
Consisting of an inverter element 9 that determines the voltage level, R/
The data input/output cover sofa is controlled together with the signal from w@ child, and the DATA terminal is switched to input, output, and high impedance modes. The address decoder generates an address in response to a synchronization signal from the CLK terminal and selects data in one of the memory cells.

The chip select signal generation circuit 5 receives a signal from the CLK terminal and outputs it as follows.

First, when a synchronizing signal (square wave) is input from the CLK terminal, charging and discharging are performed by the capacitor 7 and resistor 8 at a potential higher than the inverted potential of the inverter element 9, and the inverter element 9 receives an L level potential. Output.

Next, when there is no input of #A48 from the CLK terminal and a constant voltage is input to the chip select signal generation circuit 5, a potential lower than the inverted potential is input to the inverter element 9. The inverter element 9 outputs an H level potential.

In other words, the chip select signal generation circuit 5 outputs an L level if a synchronization signal is input, and an H level if it is not input, and can control the DATA terminal to a human power, output, and high impedance state together with the R/W signal. . Therefore, the semiconductor memory 1 can be switched between active and standby states.

〔Effect of the invention) The present invention has the following advantages.

11. The chip select signal is unnecessary, and a signal source for the chip select signal is not required when accessing the semiconductor memory.

(2) Since the number of terminals for chip select signals can be reduced, a miniaturized semiconductor memory package can be realized, and the mounting area can be reduced even when mounted on a printed circuit board or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory according to the present invention. 1...Semiconductor memory 2...Address decoder ・Memory cell ・Data input/output cover sofa ・Chip select signal generation circuit ·diode ・Capacitor ·resistance ・Inverter element Below

Claims (1)

[Claims] In semiconductor memory that inputs and outputs data serially,
A semiconductor memory having a built-in circuit that generates a control signal (chip select signal) for switching between an active state and a standby state of the semiconductor memory from a synchronization signal necessary when reading or writing the data.